mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-11 13:04:03 +08:00
arm64: soc: Xilinx SoC changes for v5.5
- Extend firmware interface to cover Versal chip -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXcPhCwAKCRDKSWXLKUoM IUL7AKCJnOr8MgplpSVBz+SvrOrIrlT2eACgmN3dakmthTjv/mzMngYN42VmxmE= =eILs -----END PGP SIGNATURE----- Merge tag 'zynqmp-soc-for-v5.5' of https://github.com/Xilinx/linux-xlnx into arm/drivers arm64: soc: Xilinx SoC changes for v5.5 - Extend firmware interface to cover Versal chip * tag 'zynqmp-soc-for-v5.5' of https://github.com/Xilinx/linux-xlnx: firmware: xilinx: Add support for versal soc dt-bindings: firmware: Add bindings for Versal firmware soc: xilinx: Set CAP_UNUSABLE requirement for versal while powering down domain Link: https://lore.kernel.org/r/6954a53c-6dab-c7a3-7257-58460ca952cb@monstr.eu Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
44a3984778
@ -11,7 +11,9 @@ power management service, FPGA service and other platform management
|
||||
services.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must contain: "xlnx,zynqmp-firmware"
|
||||
- compatible: Must contain any of below:
|
||||
"xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
|
||||
"xlnx,versal-firmware" for Versal
|
||||
- method: The method of calling the PM-API firmware layer.
|
||||
Permitted values are:
|
||||
- "smc" : SMC #0, following the SMCCC
|
||||
@ -21,6 +23,8 @@ Required properties:
|
||||
Example
|
||||
-------
|
||||
|
||||
Zynq Ultrascale+ MPSoC
|
||||
----------------------
|
||||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
compatible = "xlnx,zynqmp-firmware";
|
||||
@ -28,3 +32,13 @@ firmware {
|
||||
...
|
||||
};
|
||||
};
|
||||
|
||||
Versal
|
||||
------
|
||||
firmware {
|
||||
versal_firmware: versal-firmware {
|
||||
compatible = "xlnx,versal-firmware";
|
||||
method = "smc";
|
||||
...
|
||||
};
|
||||
};
|
||||
|
@ -711,8 +711,11 @@ static int zynqmp_firmware_probe(struct platform_device *pdev)
|
||||
int ret;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "xlnx,zynqmp");
|
||||
if (!np)
|
||||
return 0;
|
||||
if (!np) {
|
||||
np = of_find_compatible_node(NULL, NULL, "xlnx,versal");
|
||||
if (!np)
|
||||
return 0;
|
||||
}
|
||||
of_node_put(np);
|
||||
|
||||
ret = get_set_conduit_method(dev->of_node);
|
||||
@ -770,6 +773,7 @@ static int zynqmp_firmware_remove(struct platform_device *pdev)
|
||||
|
||||
static const struct of_device_id zynqmp_firmware_of_match[] = {
|
||||
{.compatible = "xlnx,zynqmp-firmware"},
|
||||
{.compatible = "xlnx,versal-firmware"},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, zynqmp_firmware_of_match);
|
||||
|
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* ZynqMP Generic PM domain support
|
||||
*
|
||||
* Copyright (C) 2015-2018 Xilinx, Inc.
|
||||
* Copyright (C) 2015-2019 Xilinx, Inc.
|
||||
*
|
||||
* Davorin Mista <davorin.mista@aggios.com>
|
||||
* Jolly Shah <jollys@xilinx.com>
|
||||
@ -25,6 +25,8 @@
|
||||
|
||||
static const struct zynqmp_eemi_ops *eemi_ops;
|
||||
|
||||
static int min_capability;
|
||||
|
||||
/**
|
||||
* struct zynqmp_pm_domain - Wrapper around struct generic_pm_domain
|
||||
* @gpd: Generic power domain
|
||||
@ -106,7 +108,7 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain)
|
||||
int ret;
|
||||
struct pm_domain_data *pdd, *tmp;
|
||||
struct zynqmp_pm_domain *pd;
|
||||
u32 capabilities = 0;
|
||||
u32 capabilities = min_capability;
|
||||
bool may_wakeup;
|
||||
|
||||
if (!eemi_ops->set_requirement)
|
||||
@ -283,6 +285,10 @@ static int zynqmp_gpd_probe(struct platform_device *pdev)
|
||||
if (!domains)
|
||||
return -ENOMEM;
|
||||
|
||||
if (!of_device_is_compatible(dev->parent->of_node,
|
||||
"xlnx,zynqmp-firmware"))
|
||||
min_capability = ZYNQMP_PM_CAPABILITY_UNUSABLE;
|
||||
|
||||
for (i = 0; i < ZYNQMP_NUM_DOMAINS; i++, pd++) {
|
||||
pd->node_id = 0;
|
||||
pd->gpd.name = kasprintf(GFP_KERNEL, "domain%d", i);
|
||||
|
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Xilinx Zynq MPSoC Firmware layer
|
||||
*
|
||||
* Copyright (C) 2014-2018 Xilinx
|
||||
* Copyright (C) 2014-2019 Xilinx
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Davorin Mista <davorin.mista@aggios.com>
|
||||
@ -46,6 +46,7 @@
|
||||
#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
|
||||
#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
|
||||
#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
|
||||
#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
|
||||
|
||||
/*
|
||||
* Firmware FPGA Manager flags
|
||||
|
Loading…
Reference in New Issue
Block a user