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ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles

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For all BG2Q SoCs, 2 cycles is the best/correct value.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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Jisheng Zhang 2014-06-12 17:38:40 +08:00 committed by Sebastian Hesselbarth
parent 7171511eae
commit 44991eb4bf
1 changed files with 2 additions and 0 deletions
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2
arch/arm/boot/dts/berlin2q.dtsi
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@ -90,6 +90,8 @@
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-level = <2>;
arm,data-latency = <2 2 2>;
arm,tag-latency = <2 2 2>;
};
scu: snoop-control-unit@ad0000 {