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dt-bindings: clock: qcom: Add SM8150 camera clock controller

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Add device tree bindings for the camera clock controller on
Qualcomm SM8150 platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240731062916.2680823-7-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Satya Priya Kakitapalli 2024-07-31 11:59:14 +05:30 committed by Bjorn Andersson
parent 8400291e28
commit 44933cd06e
2 changed files with 212 additions and 0 deletions
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77
Documentation/devicetree/bindings/clock/qcom,sm8150-camcc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SM8150
maintainers:
- Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and
power domains on SM8150.
See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
properties:
compatible:
const: qcom,sm8150-camcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Camera AHB clock from GCC
power-domains:
maxItems: 1
description:
A phandle and PM domain specifier for the MMCX power domain.
required-opps:
maxItems: 1
description:
A phandle to an OPP node describing required MMCX performance point.
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- power-domains
- required-opps
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@ad00000 {
compatible = "qcom,sm8150-camcc";
reg = <0x0ad00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_CAMERA_AHB_CLK>;
power-domains = <&rpmhpd SM8150_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

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include/dt-bindings/clock/qcom,sm8150-camcc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H
/* CAM_CC clocks */
#define CAM_CC_PLL0 0
#define CAM_CC_PLL0_OUT_EVEN 1
#define CAM_CC_PLL0_OUT_ODD 2
#define CAM_CC_PLL1 3
#define CAM_CC_PLL1_OUT_EVEN 4
#define CAM_CC_PLL2 5
#define CAM_CC_PLL2_OUT_MAIN 6
#define CAM_CC_PLL3 7
#define CAM_CC_PLL3_OUT_EVEN 8
#define CAM_CC_PLL4 9
#define CAM_CC_PLL4_OUT_EVEN 10
#define CAM_CC_BPS_AHB_CLK 11
#define CAM_CC_BPS_AREG_CLK 12
#define CAM_CC_BPS_AXI_CLK 13
#define CAM_CC_BPS_CLK 14
#define CAM_CC_BPS_CLK_SRC 15
#define CAM_CC_CAMNOC_AXI_CLK 16
#define CAM_CC_CAMNOC_AXI_CLK_SRC 17
#define CAM_CC_CAMNOC_DCD_XO_CLK 18
#define CAM_CC_CCI_0_CLK 19
#define CAM_CC_CCI_0_CLK_SRC 20
#define CAM_CC_CCI_1_CLK 21
#define CAM_CC_CCI_1_CLK_SRC 22
#define CAM_CC_CORE_AHB_CLK 23
#define CAM_CC_CPAS_AHB_CLK 24
#define CAM_CC_CPHY_RX_CLK_SRC 25
#define CAM_CC_CSI0PHYTIMER_CLK 26
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 27
#define CAM_CC_CSI1PHYTIMER_CLK 28
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 29
#define CAM_CC_CSI2PHYTIMER_CLK 30
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 31
#define CAM_CC_CSI3PHYTIMER_CLK 32
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 33
#define CAM_CC_CSIPHY0_CLK 34
#define CAM_CC_CSIPHY1_CLK 35
#define CAM_CC_CSIPHY2_CLK 36
#define CAM_CC_CSIPHY3_CLK 37
#define CAM_CC_FAST_AHB_CLK_SRC 38
#define CAM_CC_FD_CORE_CLK 39
#define CAM_CC_FD_CORE_CLK_SRC 40
#define CAM_CC_FD_CORE_UAR_CLK 41
#define CAM_CC_GDSC_CLK 42
#define CAM_CC_ICP_AHB_CLK 43
#define CAM_CC_ICP_CLK 44
#define CAM_CC_ICP_CLK_SRC 45
#define CAM_CC_IFE_0_AXI_CLK 46
#define CAM_CC_IFE_0_CLK 47
#define CAM_CC_IFE_0_CLK_SRC 48
#define CAM_CC_IFE_0_CPHY_RX_CLK 49
#define CAM_CC_IFE_0_CSID_CLK 50
#define CAM_CC_IFE_0_CSID_CLK_SRC 51
#define CAM_CC_IFE_0_DSP_CLK 52
#define CAM_CC_IFE_1_AXI_CLK 53
#define CAM_CC_IFE_1_CLK 54
#define CAM_CC_IFE_1_CLK_SRC 55
#define CAM_CC_IFE_1_CPHY_RX_CLK 56
#define CAM_CC_IFE_1_CSID_CLK 57
#define CAM_CC_IFE_1_CSID_CLK_SRC 58
#define CAM_CC_IFE_1_DSP_CLK 59
#define CAM_CC_IFE_LITE_0_CLK 60
#define CAM_CC_IFE_LITE_0_CLK_SRC 61
#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK 62
#define CAM_CC_IFE_LITE_0_CSID_CLK 63
#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC 64
#define CAM_CC_IFE_LITE_1_CLK 65
#define CAM_CC_IFE_LITE_1_CLK_SRC 66
#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK 67
#define CAM_CC_IFE_LITE_1_CSID_CLK 68
#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC 69
#define CAM_CC_IPE_0_AHB_CLK 70
#define CAM_CC_IPE_0_AREG_CLK 71
#define CAM_CC_IPE_0_AXI_CLK 72
#define CAM_CC_IPE_0_CLK 73
#define CAM_CC_IPE_0_CLK_SRC 74
#define CAM_CC_IPE_1_AHB_CLK 75
#define CAM_CC_IPE_1_AREG_CLK 76
#define CAM_CC_IPE_1_AXI_CLK 77
#define CAM_CC_IPE_1_CLK 78
#define CAM_CC_JPEG_CLK 79
#define CAM_CC_JPEG_CLK_SRC 80
#define CAM_CC_LRME_CLK 81
#define CAM_CC_LRME_CLK_SRC 82
#define CAM_CC_MCLK0_CLK 83
#define CAM_CC_MCLK0_CLK_SRC 84
#define CAM_CC_MCLK1_CLK 85
#define CAM_CC_MCLK1_CLK_SRC 86
#define CAM_CC_MCLK2_CLK 87
#define CAM_CC_MCLK2_CLK_SRC 88
#define CAM_CC_MCLK3_CLK 89
#define CAM_CC_MCLK3_CLK_SRC 90
#define CAM_CC_SLOW_AHB_CLK_SRC 91
/* CAM_CC power domains */
#define TITAN_TOP_GDSC 0
#define BPS_GDSC 1
#define IFE_0_GDSC 2
#define IFE_1_GDSC 3
#define IPE_0_GDSC 4
#define IPE_1_GDSC 5
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_CAMNOC_BCR 1
#define CAM_CC_CCI_BCR 2
#define CAM_CC_CPAS_BCR 3
#define CAM_CC_CSI0PHY_BCR 4
#define CAM_CC_CSI1PHY_BCR 5
#define CAM_CC_CSI2PHY_BCR 6
#define CAM_CC_CSI3PHY_BCR 7
#define CAM_CC_FD_BCR 8
#define CAM_CC_ICP_BCR 9
#define CAM_CC_IFE_0_BCR 10
#define CAM_CC_IFE_1_BCR 11
#define CAM_CC_IFE_LITE_0_BCR 12
#define CAM_CC_IFE_LITE_1_BCR 13
#define CAM_CC_IPE_0_BCR 14
#define CAM_CC_IPE_1_BCR 15
#define CAM_CC_JPEG_BCR 16
#define CAM_CC_LRME_BCR 17
#define CAM_CC_MCLK0_BCR 18
#define CAM_CC_MCLK1_BCR 19
#define CAM_CC_MCLK2_BCR 20
#define CAM_CC_MCLK3_BCR 21
#endif