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net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC
Introduce support for ethernet chip available in MT7988 SoC to mtk_eth_soc driver. As a first step support only the first GMAC which is hard-wired to the internal DSA switch having 4 built-in gigabit Ethernet PHYs. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/25c8377095b95d186872eeda7aa055da83e8f0ca.1690246605.git.daniel@makrotopia.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Lorenzo Bianconi
Jakub Kicinski
parent
c75e416ccf
commit
445eb6448e
@ -43,7 +43,7 @@ static const char *mtk_eth_path_name(u64 path)
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static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path)
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{
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bool updated = true;
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u32 val, mask, set;
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u32 mask, set, reg;
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switch (path) {
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case MTK_ETH_PATH_GMAC1_SGMII:
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@ -59,11 +59,13 @@ static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path)
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break;
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}
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if (updated) {
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val = mtk_r32(eth, MTK_MAC_MISC);
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val = (val & mask) | set;
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mtk_w32(eth, val, MTK_MAC_MISC);
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}
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if (mtk_is_netsys_v3_or_greater(eth))
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reg = MTK_MAC_MISC_V3;
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else
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reg = MTK_MAC_MISC;
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if (updated)
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mtk_m32(eth, mask, set, reg);
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dev_dbg(eth->dev, "path %s in %s updated = %d\n",
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mtk_eth_path_name(path), __func__, updated);
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@ -152,6 +152,54 @@ static const struct mtk_reg_map mt7986_reg_map = {
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.pse_oq_sta = 0x01a0,
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};
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static const struct mtk_reg_map mt7988_reg_map = {
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.tx_irq_mask = 0x461c,
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.tx_irq_status = 0x4618,
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.pdma = {
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.rx_ptr = 0x6900,
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.rx_cnt_cfg = 0x6904,
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.pcrx_ptr = 0x6908,
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.glo_cfg = 0x6a04,
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.rst_idx = 0x6a08,
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.delay_irq = 0x6a0c,
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.irq_status = 0x6a20,
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.irq_mask = 0x6a28,
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.adma_rx_dbg0 = 0x6a38,
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.int_grp = 0x6a50,
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},
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.qdma = {
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.qtx_cfg = 0x4400,
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.qtx_sch = 0x4404,
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.rx_ptr = 0x4500,
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.rx_cnt_cfg = 0x4504,
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.qcrx_ptr = 0x4508,
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.glo_cfg = 0x4604,
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.rst_idx = 0x4608,
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.delay_irq = 0x460c,
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.fc_th = 0x4610,
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.int_grp = 0x4620,
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.hred = 0x4644,
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.ctx_ptr = 0x4700,
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.dtx_ptr = 0x4704,
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.crx_ptr = 0x4710,
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.drx_ptr = 0x4714,
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.fq_head = 0x4720,
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.fq_tail = 0x4724,
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.fq_count = 0x4728,
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.fq_blen = 0x472c,
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.tx_sch_rate = 0x4798,
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},
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.gdm1_cnt = 0x1c00,
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.gdma_to_ppe = 0x3333,
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.ppe_base = 0x2000,
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.wdma_base = {
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[0] = 0x4800,
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[1] = 0x4c00,
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},
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.pse_iq_sta = 0x0180,
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.pse_oq_sta = 0x01a0,
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};
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/* strings used by ethtool */
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static const struct mtk_ethtool_stats {
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char str[ETH_GSTRING_LEN];
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@ -179,10 +227,54 @@ static const struct mtk_ethtool_stats {
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};
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static const char * const mtk_clks_source_name[] = {
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"ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
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"sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
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"sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
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"sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1"
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"ethif",
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"sgmiitop",
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"esw",
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"gp0",
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"gp1",
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"gp2",
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"gp3",
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"xgp1",
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"xgp2",
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"xgp3",
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"crypto",
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"fe",
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"trgpll",
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"sgmii_tx250m",
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"sgmii_rx250m",
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"sgmii_cdr_ref",
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"sgmii_cdr_fb",
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"sgmii2_tx250m",
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"sgmii2_rx250m",
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"sgmii2_cdr_ref",
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"sgmii2_cdr_fb",
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"sgmii_ck",
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"eth2pll",
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"wocpu0",
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"wocpu1",
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"netsys0",
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"netsys1",
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"ethwarp_wocpu2",
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"ethwarp_wocpu1",
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"ethwarp_wocpu0",
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"top_usxgmii0_sel",
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"top_usxgmii1_sel",
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"top_sgm0_sel",
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"top_sgm1_sel",
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"top_xfi_phy0_xtal_sel",
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"top_xfi_phy1_xtal_sel",
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"top_eth_gmii_sel",
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"top_eth_refck_50m_sel",
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"top_eth_sys_200m_sel",
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"top_eth_sys_sel",
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"top_eth_xgmii_sel",
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"top_eth_mii_sel",
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"top_netsys_sel",
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"top_netsys_500m_sel",
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"top_netsys_pao_2x_sel",
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"top_netsys_sync_250m_sel",
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"top_netsys_ppefb_250m_sel",
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"top_netsys_warp_sel",
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};
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void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
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@ -195,7 +287,7 @@ u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
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return __raw_readl(eth->base + reg);
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}
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static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
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u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg)
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{
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u32 val;
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@ -400,6 +492,19 @@ static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
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dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n");
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}
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static void mtk_setup_bridge_switch(struct mtk_eth *eth)
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{
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/* Force Port1 XGMAC Link Up */
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mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID),
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MTK_XGMAC_STS(MTK_GMAC1_ID));
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/* Adjust GSW bridge IPG to 11 */
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mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK,
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(GSW_IPG_11 << GSWTX_IPG_SHIFT) |
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(GSW_IPG_11 << GSWRX_IPG_SHIFT),
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MTK_GSW_CFG);
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}
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static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
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phy_interface_t interface)
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{
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@ -459,6 +564,8 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
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goto init_err;
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}
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break;
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case PHY_INTERFACE_MODE_INTERNAL:
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break;
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default:
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goto err_phy;
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}
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@ -528,6 +635,15 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
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return;
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}
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/* Setup gmac */
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if (mtk_is_netsys_v3_or_greater(eth) &&
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mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
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mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
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mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
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mtk_setup_bridge_switch(eth);
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}
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return;
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err_phy:
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@ -740,11 +856,15 @@ static int mtk_mdio_init(struct mtk_eth *eth)
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}
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divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
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/* Configure MDC Turbo Mode */
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if (mtk_is_netsys_v3_or_greater(eth))
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mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3);
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/* Configure MDC Divider */
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val = mtk_r32(eth, MTK_PPSC);
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val &= ~PPSC_MDC_CFG;
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val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;
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mtk_w32(eth, val, MTK_PPSC);
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val = FIELD_PREP(PPSC_MDC_CFG, divider);
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if (!mtk_is_netsys_v3_or_greater(eth))
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val |= PPSC_MDC_TURBO;
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mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC);
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dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
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@ -1205,10 +1325,19 @@ static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd,
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data |= TX_DMA_LS0;
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WRITE_ONCE(desc->txd3, data);
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if (mac->id == MTK_GMAC3_ID)
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data = PSE_GDM3_PORT;
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else
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data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
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/* set forward port */
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switch (mac->id) {
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case MTK_GMAC1_ID:
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data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2;
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break;
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case MTK_GMAC2_ID:
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data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2;
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break;
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case MTK_GMAC3_ID:
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data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2;
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break;
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}
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data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
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WRITE_ONCE(desc->txd4, data);
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@ -4387,6 +4516,17 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
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mac->phylink_config.supported_interfaces);
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}
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if (mtk_is_netsys_v3_or_greater(mac->hw) &&
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MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) &&
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id == MTK_GMAC1_ID) {
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mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
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MAC_SYM_PAUSE |
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MAC_10000FD;
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phy_interface_zero(mac->phylink_config.supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_INTERNAL,
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mac->phylink_config.supported_interfaces);
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}
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phylink = phylink_create(&mac->phylink_config,
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of_fwnode_handle(mac->of_node),
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phy_mode, &mtk_phylink_ops);
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@ -4913,6 +5053,24 @@ static const struct mtk_soc_data mt7986_data = {
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},
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};
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static const struct mtk_soc_data mt7988_data = {
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.reg_map = &mt7988_reg_map,
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.ana_rgc3 = 0x128,
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.caps = MT7988_CAPS,
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.hw_features = MTK_HW_FEATURES,
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.required_clks = MT7988_CLKS_BITMAP,
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.required_pctl = false,
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.version = 3,
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.txrx = {
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.txd_size = sizeof(struct mtk_tx_dma_v2),
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.rxd_size = sizeof(struct mtk_rx_dma_v2),
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.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
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.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
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.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
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.dma_len_offset = 8,
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},
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};
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static const struct mtk_soc_data rt5350_data = {
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.reg_map = &mt7628_reg_map,
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.caps = MT7628_CAPS,
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@ -4931,14 +5089,15 @@ static const struct mtk_soc_data rt5350_data = {
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};
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const struct of_device_id of_mtk_match[] = {
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{ .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
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{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
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{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
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{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
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{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
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{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data},
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{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
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{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
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{ .compatible = "mediatek,mt2701-eth", .data = &mt2701_data },
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{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
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{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data },
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{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
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{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
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{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
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{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
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{ .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
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{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
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{},
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};
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MODULE_DEVICE_TABLE(of, of_mtk_match);
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@ -117,7 +117,8 @@
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#define MTK_CDMP_EG_CTRL 0x404
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/* GDM Exgress Control Register */
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#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
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#define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
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0x540 : 0x500 + (_x * 0x1000); })
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#define MTK_GDMA_SPECIAL_TAG BIT(24)
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#define MTK_GDMA_ICS_EN BIT(22)
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#define MTK_GDMA_TCS_EN BIT(21)
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@ -126,6 +127,11 @@
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#define MTK_GDMA_TO_PDMA 0x0
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#define MTK_GDMA_DROP_ALL 0x7777
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/* GDM Egress Control Register */
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#define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
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0x544 : 0x504 + (_x * 0x1000); })
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#define MTK_GDMA_XGDM_SEL BIT(31)
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/* Unicast Filter MAC Address Register - Low */
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#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
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@ -389,7 +395,26 @@
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#define PHY_IAC_TIMEOUT HZ
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#define MTK_MAC_MISC 0x1000c
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#define MTK_MAC_MISC_V3 0x10010
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#define MTK_MUX_TO_ESW BIT(0)
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#define MISC_MDC_TURBO BIT(4)
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/* XMAC status registers */
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#define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C)
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#define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15))
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#define MTK_USXGMII_PCS_LINK BIT(8)
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#define MTK_XGMAC_RX_FC BIT(5)
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#define MTK_XGMAC_TX_FC BIT(4)
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#define MTK_USXGMII_PCS_MODE GENMASK(3, 1)
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#define MTK_XGMAC_LINK_STS BIT(0)
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/* GSW bridge registers */
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#define MTK_GSW_CFG (0x10080)
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#define GSWTX_IPG_MASK GENMASK(19, 16)
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#define GSWTX_IPG_SHIFT 16
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#define GSWRX_IPG_MASK GENMASK(3, 0)
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#define GSWRX_IPG_SHIFT 0
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#define GSW_IPG_11 11
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/* Mac control registers */
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#define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
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@ -647,6 +672,11 @@ enum mtk_clks_map {
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MTK_CLK_GP0,
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MTK_CLK_GP1,
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MTK_CLK_GP2,
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MTK_CLK_GP3,
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MTK_CLK_XGP1,
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MTK_CLK_XGP2,
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MTK_CLK_XGP3,
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MTK_CLK_CRYPTO,
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MTK_CLK_FE,
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MTK_CLK_TRGPLL,
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MTK_CLK_SGMII_TX_250M,
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@ -663,6 +693,27 @@ enum mtk_clks_map {
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MTK_CLK_WOCPU1,
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MTK_CLK_NETSYS0,
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MTK_CLK_NETSYS1,
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MTK_CLK_ETHWARP_WOCPU2,
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MTK_CLK_ETHWARP_WOCPU1,
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MTK_CLK_ETHWARP_WOCPU0,
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MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
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MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
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MTK_CLK_TOP_SGM_0_SEL,
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MTK_CLK_TOP_SGM_1_SEL,
|
||||
MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
|
||||
MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
|
||||
MTK_CLK_TOP_ETH_GMII_SEL,
|
||||
MTK_CLK_TOP_ETH_REFCK_50M_SEL,
|
||||
MTK_CLK_TOP_ETH_SYS_200M_SEL,
|
||||
MTK_CLK_TOP_ETH_SYS_SEL,
|
||||
MTK_CLK_TOP_ETH_XGMII_SEL,
|
||||
MTK_CLK_TOP_ETH_MII_SEL,
|
||||
MTK_CLK_TOP_NETSYS_SEL,
|
||||
MTK_CLK_TOP_NETSYS_500M_SEL,
|
||||
MTK_CLK_TOP_NETSYS_PAO_2X_SEL,
|
||||
MTK_CLK_TOP_NETSYS_SYNC_250M_SEL,
|
||||
MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL,
|
||||
MTK_CLK_TOP_NETSYS_WARP_SEL,
|
||||
MTK_CLK_MAX
|
||||
};
|
||||
|
||||
@ -716,6 +767,36 @@ enum mtk_clks_map {
|
||||
BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
|
||||
BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
|
||||
BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
|
||||
#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
|
||||
BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
|
||||
BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
|
||||
BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
|
||||
BIT_ULL(MTK_CLK_CRYPTO) | \
|
||||
BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
|
||||
BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
|
||||
BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
|
||||
BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
|
||||
BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
|
||||
BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
|
||||
BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
|
||||
BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL))
|
||||
|
||||
enum mtk_dev_state {
|
||||
MTK_HW_INIT,
|
||||
@ -964,6 +1045,8 @@ enum mkt_eth_capabilities {
|
||||
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
|
||||
MTK_RSTCTRL_PPE1)
|
||||
|
||||
#define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1)
|
||||
|
||||
struct mtk_tx_dma_desc_info {
|
||||
dma_addr_t addr;
|
||||
u32 size;
|
||||
@ -1309,6 +1392,7 @@ void mtk_stats_update_mac(struct mtk_mac *mac);
|
||||
|
||||
void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
|
||||
u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
|
||||
u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
|
||||
|
||||
int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
|
||||
int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user