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mtd: nand: fsmc: remove stale non-DT probe path
The FSMC driver has an execution path and a header file in <linux/mtd/fsmc.h> that serves to support passing in platform data through board files, albeit no upstream users of this mechanism exist. The header file also contains function headers for functions that do not exist in the kernel. Delete this and move the platform data struct, parsing and handling into the driver, assume we are using OF and make the driver depend on OF, remove the ifdefs making that optional. Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Stefan Roese <sr@denx.de> Cc: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Linus Walleij
Boris Brezillon
parent
4339b7fdbb
commit
4404d7d821
@ -535,6 +535,7 @@ config MTD_NAND_JZ4780
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config MTD_NAND_FSMC
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tristate "Support for NAND on ST Micros FSMC"
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depends on OF
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depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300
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help
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Enables support for NAND Flash chips on the ST Microelectronics
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@ -35,10 +35,133 @@
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#include <linux/mtd/partitions.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/mtd/fsmc.h>
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#include <linux/amba/bus.h>
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#include <mtd/mtd-abi.h>
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#define FSMC_NAND_BW8 1
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#define FSMC_NAND_BW16 2
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#define FSMC_MAX_NOR_BANKS 4
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#define FSMC_MAX_NAND_BANKS 4
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#define FSMC_FLASH_WIDTH8 1
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#define FSMC_FLASH_WIDTH16 2
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/* fsmc controller registers for NOR flash */
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#define CTRL 0x0
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/* ctrl register definitions */
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#define BANK_ENABLE (1 << 0)
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#define MUXED (1 << 1)
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#define NOR_DEV (2 << 2)
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#define WIDTH_8 (0 << 4)
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#define WIDTH_16 (1 << 4)
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#define RSTPWRDWN (1 << 6)
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#define WPROT (1 << 7)
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#define WRT_ENABLE (1 << 12)
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#define WAIT_ENB (1 << 13)
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#define CTRL_TIM 0x4
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/* ctrl_tim register definitions */
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#define FSMC_NOR_BANK_SZ 0x8
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#define FSMC_NOR_REG_SIZE 0x40
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#define FSMC_NOR_REG(base, bank, reg) (base + \
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FSMC_NOR_BANK_SZ * (bank) + \
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reg)
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/* fsmc controller registers for NAND flash */
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#define PC 0x00
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/* pc register definitions */
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#define FSMC_RESET (1 << 0)
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#define FSMC_WAITON (1 << 1)
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#define FSMC_ENABLE (1 << 2)
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#define FSMC_DEVTYPE_NAND (1 << 3)
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#define FSMC_DEVWID_8 (0 << 4)
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#define FSMC_DEVWID_16 (1 << 4)
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#define FSMC_ECCEN (1 << 6)
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#define FSMC_ECCPLEN_512 (0 << 7)
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#define FSMC_ECCPLEN_256 (1 << 7)
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#define FSMC_TCLR_1 (1)
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#define FSMC_TCLR_SHIFT (9)
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#define FSMC_TCLR_MASK (0xF)
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#define FSMC_TAR_1 (1)
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#define FSMC_TAR_SHIFT (13)
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#define FSMC_TAR_MASK (0xF)
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#define STS 0x04
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/* sts register definitions */
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#define FSMC_CODE_RDY (1 << 15)
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#define COMM 0x08
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/* comm register definitions */
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#define FSMC_TSET_0 0
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#define FSMC_TSET_SHIFT 0
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#define FSMC_TSET_MASK 0xFF
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#define FSMC_TWAIT_6 6
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#define FSMC_TWAIT_SHIFT 8
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#define FSMC_TWAIT_MASK 0xFF
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#define FSMC_THOLD_4 4
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#define FSMC_THOLD_SHIFT 16
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#define FSMC_THOLD_MASK 0xFF
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#define FSMC_THIZ_1 1
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#define FSMC_THIZ_SHIFT 24
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#define FSMC_THIZ_MASK 0xFF
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#define ATTRIB 0x0C
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#define IOATA 0x10
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#define ECC1 0x14
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#define ECC2 0x18
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#define ECC3 0x1C
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#define FSMC_NAND_BANK_SZ 0x20
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#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
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(FSMC_NAND_BANK_SZ * (bank)) + \
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reg)
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#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
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struct fsmc_nand_timings {
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uint8_t tclr;
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uint8_t tar;
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uint8_t thiz;
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uint8_t thold;
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uint8_t twait;
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uint8_t tset;
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};
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enum access_mode {
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USE_DMA_ACCESS = 1,
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USE_WORD_ACCESS,
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};
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/**
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* fsmc_nand_platform_data - platform specific NAND controller config
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* @nand_timings: timing setup for the physical NAND interface
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* @partitions: partition table for the platform, use a default fallback
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* if this is NULL
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* @nr_partitions: the number of partitions in the previous entry
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* @options: different options for the driver
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* @width: bus width
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* @bank: default bank
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* @select_bank: callback to select a certain bank, this is
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* platform-specific. If the controller only supports one bank
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* this may be set to NULL
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*/
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struct fsmc_nand_platform_data {
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struct fsmc_nand_timings *nand_timings;
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struct mtd_partition *partitions;
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unsigned int nr_partitions;
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unsigned int options;
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unsigned int width;
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unsigned int bank;
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enum access_mode mode;
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void (*select_bank)(uint32_t bank, uint32_t busw);
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/* priv structures for dma accesses */
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void *read_dma_priv;
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void *write_dma_priv;
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};
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static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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@ -714,7 +837,6 @@ static bool filter(struct dma_chan *chan, void *slave)
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return true;
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}
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#ifdef CONFIG_OF
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static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
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struct device_node *np)
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{
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@ -757,13 +879,6 @@ static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
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}
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return 0;
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}
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#else
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static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
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struct device_node *np)
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{
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return -ENOSYS;
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}
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#endif
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/*
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* fsmc_nand_probe - Probe function
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@ -782,19 +897,15 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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u32 pid;
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int i;
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if (np) {
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pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
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pdev->dev.platform_data = pdata;
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ret = fsmc_nand_probe_config_dt(pdev, np);
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if (ret) {
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dev_err(&pdev->dev, "no platform data\n");
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return -ENODEV;
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}
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}
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pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return -ENOMEM;
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if (!pdata) {
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dev_err(&pdev->dev, "platform data is NULL\n");
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return -EINVAL;
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pdev->dev.platform_data = pdata;
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ret = fsmc_nand_probe_config_dt(pdev, np);
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if (ret) {
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dev_err(&pdev->dev, "no platform data\n");
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return -ENODEV;
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}
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/* Allocate memory for the device structure (and zero it) */
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@ -1,156 +0,0 @@
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/*
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* incude/mtd/fsmc.h
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*
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* ST Microelectronics
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* Flexible Static Memory Controller (FSMC)
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* platform data interface and header file
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*
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* Copyright © 2010 ST Microelectronics
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* Vipin Kumar <vipin.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __MTD_FSMC_H
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#define __MTD_FSMC_H
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <linux/types.h>
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#include <linux/mtd/partitions.h>
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#include <asm/param.h>
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#define FSMC_NAND_BW8 1
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#define FSMC_NAND_BW16 2
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#define FSMC_MAX_NOR_BANKS 4
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#define FSMC_MAX_NAND_BANKS 4
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#define FSMC_FLASH_WIDTH8 1
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#define FSMC_FLASH_WIDTH16 2
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/* fsmc controller registers for NOR flash */
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#define CTRL 0x0
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/* ctrl register definitions */
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#define BANK_ENABLE (1 << 0)
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#define MUXED (1 << 1)
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#define NOR_DEV (2 << 2)
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#define WIDTH_8 (0 << 4)
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#define WIDTH_16 (1 << 4)
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#define RSTPWRDWN (1 << 6)
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#define WPROT (1 << 7)
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#define WRT_ENABLE (1 << 12)
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#define WAIT_ENB (1 << 13)
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#define CTRL_TIM 0x4
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/* ctrl_tim register definitions */
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#define FSMC_NOR_BANK_SZ 0x8
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#define FSMC_NOR_REG_SIZE 0x40
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#define FSMC_NOR_REG(base, bank, reg) (base + \
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FSMC_NOR_BANK_SZ * (bank) + \
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reg)
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/* fsmc controller registers for NAND flash */
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#define PC 0x00
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/* pc register definitions */
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#define FSMC_RESET (1 << 0)
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#define FSMC_WAITON (1 << 1)
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#define FSMC_ENABLE (1 << 2)
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#define FSMC_DEVTYPE_NAND (1 << 3)
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#define FSMC_DEVWID_8 (0 << 4)
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#define FSMC_DEVWID_16 (1 << 4)
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#define FSMC_ECCEN (1 << 6)
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#define FSMC_ECCPLEN_512 (0 << 7)
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#define FSMC_ECCPLEN_256 (1 << 7)
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#define FSMC_TCLR_1 (1)
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#define FSMC_TCLR_SHIFT (9)
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#define FSMC_TCLR_MASK (0xF)
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#define FSMC_TAR_1 (1)
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#define FSMC_TAR_SHIFT (13)
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#define FSMC_TAR_MASK (0xF)
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#define STS 0x04
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/* sts register definitions */
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#define FSMC_CODE_RDY (1 << 15)
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#define COMM 0x08
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/* comm register definitions */
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#define FSMC_TSET_0 0
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#define FSMC_TSET_SHIFT 0
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#define FSMC_TSET_MASK 0xFF
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#define FSMC_TWAIT_6 6
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#define FSMC_TWAIT_SHIFT 8
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#define FSMC_TWAIT_MASK 0xFF
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#define FSMC_THOLD_4 4
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#define FSMC_THOLD_SHIFT 16
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#define FSMC_THOLD_MASK 0xFF
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#define FSMC_THIZ_1 1
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#define FSMC_THIZ_SHIFT 24
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#define FSMC_THIZ_MASK 0xFF
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#define ATTRIB 0x0C
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#define IOATA 0x10
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#define ECC1 0x14
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#define ECC2 0x18
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#define ECC3 0x1C
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#define FSMC_NAND_BANK_SZ 0x20
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#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
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(FSMC_NAND_BANK_SZ * (bank)) + \
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reg)
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#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
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struct fsmc_nand_timings {
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uint8_t tclr;
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uint8_t tar;
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uint8_t thiz;
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uint8_t thold;
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uint8_t twait;
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uint8_t tset;
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};
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enum access_mode {
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USE_DMA_ACCESS = 1,
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USE_WORD_ACCESS,
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};
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/**
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* fsmc_nand_platform_data - platform specific NAND controller config
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* @nand_timings: timing setup for the physical NAND interface
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* @partitions: partition table for the platform, use a default fallback
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* if this is NULL
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* @nr_partitions: the number of partitions in the previous entry
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* @options: different options for the driver
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* @width: bus width
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* @bank: default bank
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* @select_bank: callback to select a certain bank, this is
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* platform-specific. If the controller only supports one bank
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* this may be set to NULL
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*/
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struct fsmc_nand_platform_data {
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struct fsmc_nand_timings *nand_timings;
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struct mtd_partition *partitions;
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unsigned int nr_partitions;
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unsigned int options;
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unsigned int width;
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unsigned int bank;
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enum access_mode mode;
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void (*select_bank)(uint32_t bank, uint32_t busw);
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/* priv structures for dma accesses */
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void *read_dma_priv;
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void *write_dma_priv;
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};
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extern int __init fsmc_nor_init(struct platform_device *pdev,
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unsigned long base, uint32_t bank, uint32_t width);
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extern void __init fsmc_init_board_info(struct platform_device *pdev,
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struct mtd_partition *partitions, unsigned int nr_partitions,
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unsigned int width);
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#endif /* __MTD_FSMC_H */
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