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perf/x86: Add hardware events translations for Intel cpus
Add support for Intel processors to display 'events' sysfs directory (/sys/devices/cpu/events/) with hw event translations: # ls /sys/devices/cpu/events/ branch-instructions branch-misses bus-cycles cache-misses cache-references cpu-cycles instructions ref-cycles stalled-cycles-backend stalled-cycles-frontend Suggested-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Signed-off-by: Jiri Olsa <jolsa@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: Paul Mackerras <paulus@samba.org> Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Stephane Eranian <eranian@google.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1349873598-12583-4-git-send-email-jolsa@redhat.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -1392,6 +1392,46 @@ static struct attribute_group x86_pmu_events_group = {
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.attrs = events_attr,
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};
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ssize_t x86_event_sysfs_show(char *page, u64 config)
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{
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u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
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u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
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u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
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bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
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bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
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bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
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bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
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ssize_t ret;
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/*
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* We have whole page size to spend and just little data
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* to write, so we can safely use sprintf.
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*/
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ret = sprintf(page, "event=0x%02llx", event);
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if (umask)
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ret += sprintf(page + ret, ",umask=0x%02llx", umask);
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if (edge)
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ret += sprintf(page + ret, ",edge");
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if (pc)
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ret += sprintf(page + ret, ",pc");
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if (any)
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ret += sprintf(page + ret, ",any");
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if (inv)
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ret += sprintf(page + ret, ",inv");
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if (cmask)
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ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
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ret += sprintf(page + ret, "\n");
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return ret;
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}
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static int __init init_hw_perf_events(void)
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{
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struct x86_pmu_quirk *quirk;
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@ -538,6 +538,8 @@ static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
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regs->ip = ip;
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}
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ssize_t x86_event_sysfs_show(char *page, u64 config);
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#ifdef CONFIG_CPU_SUP_AMD
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int amd_pmu_init(void);
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@ -1628,6 +1628,7 @@ static __initconst const struct x86_pmu core_pmu = {
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.event_constraints = intel_core_event_constraints,
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.guest_get_msrs = core_guest_get_msrs,
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.format_attrs = intel_arch_formats_attr,
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.events_sysfs_show = x86_event_sysfs_show,
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};
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struct intel_shared_regs *allocate_shared_regs(int cpu)
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@ -1766,6 +1767,7 @@ static __initconst const struct x86_pmu intel_pmu = {
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.pebs_aliases = intel_pebs_aliases_core2,
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.format_attrs = intel_arch3_formats_attr,
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.events_sysfs_show = x86_event_sysfs_show,
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.cpu_prepare = intel_pmu_cpu_prepare,
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.cpu_starting = intel_pmu_cpu_starting,
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