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arm64: cpu_errata: Add Hisilicon TSV110 to spectre-v2 safe list

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[ Upstream commit aa638cfe3e ]

HiSilicon Taishan v110 CPUs didn't implement CSV2 field of the
ID_AA64PFR0_EL1, but spectre-v2 is mitigated by hardware, so
whitelist the MIDR in the safe list.

Signed-off-by: Wei Li <liwei391@huawei.com>
[hanjun: re-write the commit log]
Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Wei Li 2019-12-20 17:17:10 +08:00 committed by Greg Kroah-Hartman
parent 542dc09cc5
commit 43b0b33009
1 changed files with 1 additions and 0 deletions
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arch/arm64/kernel/cpu_errata.c
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@ -575,6 +575,7 @@ static const struct midr_range spectre_v2_safe_list[] = {
MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
{ /* sentinel */ }
};