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atl1c: Atheros L1C Gigabit Ethernet driver

Browse Source 
Supporting AR8131, and AR8132.

Signed-off-by: Jie Yang <jie.yang@atheros.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jie Yang 2009-02-18 17:24:15 -08:00 committed by David S. Miller
parent 92a0acce18
commit 43250ddd75
8 changed files with 5120 additions and 0 deletions
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11
drivers/net/Kconfig
View File

@ -2342,6 +2342,17 @@ config ATL1E
To compile this driver as a module, choose M here. The module
will be called atl1e.
config ATL1C
tristate "Atheros L1C Gigabit Ethernet support (EXPERIMENTAL)"
depends on PCI && EXPERIMENTAL
select CRC32
select MII
help
This driver supports the Atheros L1C gigabit ethernet adapter.
To compile this driver as a module, choose M here. The module
will be called atl1c.
config JME
tristate "JMicron(R) PCI-Express Gigabit Ethernet support"
depends on PCI

1
drivers/net/Makefile
View File

@ -17,6 +17,7 @@ obj-$(CONFIG_BONDING) += bonding/
obj-$(CONFIG_ATL1) += atlx/
obj-$(CONFIG_ATL2) += atlx/
obj-$(CONFIG_ATL1E) += atl1e/
obj-$(CONFIG_ATL1C) += atl1c/
obj-$(CONFIG_GIANFAR) += gianfar_driver.o
obj-$(CONFIG_TEHUTI) += tehuti.o
obj-$(CONFIG_ENIC) += enic/

2
drivers/net/atl1c/Makefile Normal file
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@ -0,0 +1,2 @@
obj-$(CONFIG_ATL1C) += atl1c.o
atl1c-objs := atl1c_main.o atl1c_hw.o atl1c_ethtool.o

606
drivers/net/atl1c/atl1c.h Normal file
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@ -0,0 +1,606 @@
/*
* Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
*
* Derived from Intel e1000 driver
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _ATL1C_H_
#define _ATL1C_H_
#include <linux/version.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/in.h>
#include <linux/ip.h>
#include <linux/ipv6.h>
#include <linux/udp.h>
#include <linux/mii.h>
#include <linux/io.h>
#include <linux/vmalloc.h>
#include <linux/pagemap.h>
#include <linux/tcp.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/if_vlan.h>
#include <linux/workqueue.h>
#include <net/checksum.h>
#include <net/ip6_checksum.h>
#include "atl1c_hw.h"
/* Wake Up Filter Control */
#define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
#define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
#define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
#define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
#define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
#define AT_VLAN_TO_TAG(_vlan, _tag) \
_tag = ((((_vlan) >> 8) & 0xFF) |\
(((_vlan) & 0xFF) << 8))
#define AT_TAG_TO_VLAN(_tag, _vlan) \
_vlan = ((((_tag) >> 8) & 0xFF) |\
(((_tag) & 0xFF) << 8))
#define SPEED_0 0xffff
#define HALF_DUPLEX 1
#define FULL_DUPLEX 2
#define AT_RX_BUF_SIZE (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)
#define MAX_JUMBO_FRAME_SIZE (9*1024)
#define MAX_TX_OFFLOAD_THRESH (9*1024)
#define AT_MAX_RECEIVE_QUEUE 4
#define AT_DEF_RECEIVE_QUEUE 1
#define AT_MAX_TRANSMIT_QUEUE 2
#define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL
#define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL
#define AT_TX_WATCHDOG (5 * HZ)
#define AT_MAX_INT_WORK 5
#define AT_TWSI_EEPROM_TIMEOUT 100
#define AT_HW_MAX_IDLE_DELAY 10
#define AT_SUSPEND_LINK_TIMEOUT 28
#define AT_ASPM_L0S_TIMER 6
#define AT_ASPM_L1_TIMER 12
#define ATL1C_PCIE_L0S_L1_DISABLE 0x01
#define ATL1C_PCIE_PHY_RESET 0x02
#define ATL1C_ASPM_L0s_ENABLE 0x0001
#define ATL1C_ASPM_L1_ENABLE 0x0002
#define AT_REGS_LEN (75 * sizeof(u32))
#define AT_EEPROM_LEN 512
#define ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
#define ATL1C_RFD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc)
#define ATL1C_TPD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc)
#define ATL1C_RRD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status)
/* tpd word 1 bit 0:7 General Checksum task offload */
#define TPD_L4HDR_OFFSET_MASK 0x00FF
#define TPD_L4HDR_OFFSET_SHIFT 0
/* tpd word 1 bit 0:7 Large Send task offload (IPv4/IPV6) */
#define TPD_TCPHDR_OFFSET_MASK 0x00FF
#define TPD_TCPHDR_OFFSET_SHIFT 0
/* tpd word 1 bit 0:7 Custom Checksum task offload */
#define TPD_PLOADOFFSET_MASK 0x00FF
#define TPD_PLOADOFFSET_SHIFT 0
/* tpd word 1 bit 8:17 */
#define TPD_CCSUM_EN_MASK 0x0001
#define TPD_CCSUM_EN_SHIFT 8
#define TPD_IP_CSUM_MASK 0x0001
#define TPD_IP_CSUM_SHIFT 9
#define TPD_TCP_CSUM_MASK 0x0001
#define TPD_TCP_CSUM_SHIFT 10
#define TPD_UDP_CSUM_MASK 0x0001
#define TPD_UDP_CSUM_SHIFT 11
#define TPD_LSO_EN_MASK 0x0001 /* TCP Large Send Offload */
#define TPD_LSO_EN_SHIFT 12
#define TPD_LSO_VER_MASK 0x0001
#define TPD_LSO_VER_SHIFT 13 /* 0 : ipv4; 1 : ipv4/ipv6 */
#define TPD_CON_VTAG_MASK 0x0001
#define TPD_CON_VTAG_SHIFT 14
#define TPD_INS_VTAG_MASK 0x0001
#define TPD_INS_VTAG_SHIFT 15
#define TPD_IPV4_PACKET_MASK 0x0001 /* valid when LSO VER is 1 */
#define TPD_IPV4_PACKET_SHIFT 16
#define TPD_ETH_TYPE_MASK 0x0001
#define TPD_ETH_TYPE_SHIFT 17 /* 0 : 802.3 frame; 1 : Ethernet */
/* tpd word 18:25 Custom Checksum task offload */
#define TPD_CCSUM_OFFSET_MASK 0x00FF
#define TPD_CCSUM_OFFSET_SHIFT 18
#define TPD_CCSUM_EPAD_MASK 0x0001
#define TPD_CCSUM_EPAD_SHIFT 30
/* tpd word 18:30 Large Send task offload (IPv4/IPV6) */
#define TPD_MSS_MASK 0x1FFF
#define TPD_MSS_SHIFT 18
#define TPD_EOP_MASK 0x0001
#define TPD_EOP_SHIFT 31
struct atl1c_tpd_desc {
__le16 buffer_len; /* include 4-byte CRC */
__le16 vlan_tag;
__le32 word1;
__le64 buffer_addr;
};
struct atl1c_tpd_ext_desc {
u32 reservd_0;
__le32 word1;
__le32 pkt_len;
u32 reservd_1;
};
/* rrs word 0 bit 0:31 */
#define RRS_RX_CSUM_MASK 0xFFFF
#define RRS_RX_CSUM_SHIFT 0
#define RRS_RX_RFD_CNT_MASK 0x000F
#define RRS_RX_RFD_CNT_SHIFT 16
#define RRS_RX_RFD_INDEX_MASK 0x0FFF
#define RRS_RX_RFD_INDEX_SHIFT 20
/* rrs flag bit 0:16 */
#define RRS_HEAD_LEN_MASK 0x00FF
#define RRS_HEAD_LEN_SHIFT 0
#define RRS_HDS_TYPE_MASK 0x0003
#define RRS_HDS_TYPE_SHIFT 8
#define RRS_CPU_NUM_MASK 0x0003
#define RRS_CPU_NUM_SHIFT 10
#define RRS_HASH_FLG_MASK 0x000F
#define RRS_HASH_FLG_SHIFT 12
#define RRS_HDS_TYPE_HEAD 1
#define RRS_HDS_TYPE_DATA 2
#define RRS_IS_NO_HDS_TYPE(flag) \
(((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == 0)
#define RRS_IS_HDS_HEAD(flag) \
(((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == \
RRS_HDS_TYPE_HEAD)
#define RRS_IS_HDS_DATA(flag) \
(((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == \
RRS_HDS_TYPE_DATA)
/* rrs word 3 bit 0:31 */
#define RRS_PKT_SIZE_MASK 0x3FFF
#define RRS_PKT_SIZE_SHIFT 0
#define RRS_ERR_L4_CSUM_MASK 0x0001
#define RRS_ERR_L4_CSUM_SHIFT 14
#define RRS_ERR_IP_CSUM_MASK 0x0001
#define RRS_ERR_IP_CSUM_SHIFT 15
#define RRS_VLAN_INS_MASK 0x0001
#define RRS_VLAN_INS_SHIFT 16
#define RRS_PROT_ID_MASK 0x0007
#define RRS_PROT_ID_SHIFT 17
#define RRS_RX_ERR_SUM_MASK 0x0001
#define RRS_RX_ERR_SUM_SHIFT 20
#define RRS_RX_ERR_CRC_MASK 0x0001
#define RRS_RX_ERR_CRC_SHIFT 21
#define RRS_RX_ERR_FAE_MASK 0x0001
#define RRS_RX_ERR_FAE_SHIFT 22
#define RRS_RX_ERR_TRUNC_MASK 0x0001
#define RRS_RX_ERR_TRUNC_SHIFT 23
#define RRS_RX_ERR_RUNC_MASK 0x0001
#define RRS_RX_ERR_RUNC_SHIFT 24
#define RRS_RX_ERR_ICMP_MASK 0x0001
#define RRS_RX_ERR_ICMP_SHIFT 25
#define RRS_PACKET_BCAST_MASK 0x0001
#define RRS_PACKET_BCAST_SHIFT 26
#define RRS_PACKET_MCAST_MASK 0x0001
#define RRS_PACKET_MCAST_SHIFT 27
#define RRS_PACKET_TYPE_MASK 0x0001
#define RRS_PACKET_TYPE_SHIFT 28
#define RRS_FIFO_FULL_MASK 0x0001
#define RRS_FIFO_FULL_SHIFT 29
#define RRS_802_3_LEN_ERR_MASK 0x0001
#define RRS_802_3_LEN_ERR_SHIFT 30
#define RRS_RXD_UPDATED_MASK 0x0001
#define RRS_RXD_UPDATED_SHIFT 31
#define RRS_ERR_L4_CSUM 0x00004000
#define RRS_ERR_IP_CSUM 0x00008000
#define RRS_VLAN_INS 0x00010000
#define RRS_RX_ERR_SUM 0x00100000
#define RRS_RX_ERR_CRC 0x00200000
#define RRS_802_3_LEN_ERR 0x40000000
#define RRS_RXD_UPDATED 0x80000000
#define RRS_PACKET_TYPE_802_3 1
#define RRS_PACKET_TYPE_ETH 0
#define RRS_PACKET_IS_ETH(word) \
(((word) >> RRS_PACKET_TYPE_SHIFT) & RRS_PACKET_TYPE_MASK == \
RRS_PACKET_TYPE_ETH)
#define RRS_RXD_IS_VALID(word) \
((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1)
#define RRS_PACKET_PROT_IS_IPV4_ONLY(word) \
((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1)
#define RRS_PACKET_PROT_IS_IPV6_ONLY(word) \
((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6)
struct atl1c_recv_ret_status {
__le32 word0;
__le32 rss_hash;
__le16 vlan_tag;
__le16 flag;
__le32 word3;
};
/* RFD desciptor */
struct atl1c_rx_free_desc {
__le64 buffer_addr;
};
/* DMA Order Settings */
enum atl1c_dma_order {
atl1c_dma_ord_in = 1,
atl1c_dma_ord_enh = 2,
atl1c_dma_ord_out = 4
};
enum atl1c_dma_rcb {
atl1c_rcb_64 = 0,
atl1c_rcb_128 = 1
};
enum atl1c_mac_speed {
atl1c_mac_speed_0 = 0,
atl1c_mac_speed_10_100 = 1,
atl1c_mac_speed_1000 = 2
};
enum atl1c_dma_req_block {
atl1c_dma_req_128 = 0,
atl1c_dma_req_256 = 1,
atl1c_dma_req_512 = 2,
atl1c_dma_req_1024 = 3,
atl1c_dma_req_2048 = 4,
atl1c_dma_req_4096 = 5
};
enum atl1c_rss_mode {
atl1c_rss_mode_disable = 0,
atl1c_rss_sig_que = 1,
atl1c_rss_mul_que_sig_int = 2,
atl1c_rss_mul_que_mul_int = 4,
};
enum atl1c_rss_type {
atl1c_rss_disable = 0,
atl1c_rss_ipv4 = 1,
atl1c_rss_ipv4_tcp = 2,
atl1c_rss_ipv6 = 4,
atl1c_rss_ipv6_tcp = 8
};
enum atl1c_nic_type {
athr_l1c = 0,
athr_l2c = 1,
};
enum atl1c_trans_queue {
atl1c_trans_normal = 0,
atl1c_trans_high = 1
};
struct atl1c_hw_stats {
/* rx */
unsigned long rx_ok; /* The number of good packet received. */
unsigned long rx_bcast; /* The number of good broadcast packet received. */
unsigned long rx_mcast; /* The number of good multicast packet received. */
unsigned long rx_pause; /* The number of Pause packet received. */
unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */
unsigned long rx_fcs_err; /* The number of packets with bad FCS. */
unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */
unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
unsigned long rx_align_err; /* Alignment Error */
unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */
/* tx */
unsigned long tx_ok; /* The number of good packet transmitted. */
unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */
unsigned long tx_mcast; /* The number of good multicast packet transmitted. */
unsigned long tx_pause; /* The number of Pause packet transmitted. */
unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
unsigned long tx_defer; /* The number of packets transmitted that is deferred. */
unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */
unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
};
struct atl1c_hw {
u8 __iomem *hw_addr; /* inner register address */
struct atl1c_adapter *adapter;
enum atl1c_nic_type nic_type;
enum atl1c_dma_order dma_order;
enum atl1c_dma_rcb rcb_value;
enum atl1c_dma_req_block dmar_block;
enum atl1c_dma_req_block dmaw_block;
u16 device_id;
u16 vendor_id;
u16 subsystem_id;
u16 subsystem_vendor_id;
u8 revision_id;
u32 intr_mask;
u8 dmaw_dly_cnt;
u8 dmar_dly_cnt;
u8 preamble_len;
u16 max_frame_size;
u16 min_frame_size;
enum atl1c_mac_speed mac_speed;
bool mac_duplex;
bool hibernate;
u16 media_type;
#define MEDIA_TYPE_AUTO_SENSOR 0
#define MEDIA_TYPE_100M_FULL 1
#define MEDIA_TYPE_100M_HALF 2
#define MEDIA_TYPE_10M_FULL 3
#define MEDIA_TYPE_10M_HALF 4
u16 autoneg_advertised;
u16 mii_autoneg_adv_reg;
u16 mii_1000t_ctrl_reg;
u16 tx_imt; /* TX Interrupt Moderator timer ( 2us resolution) */
u16 rx_imt; /* RX Interrupt Moderator timer ( 2us resolution) */
u16 ict; /* Interrupt Clear timer (2us resolution) */
u16 ctrl_flags;
#define ATL1C_INTR_CLEAR_ON_READ 0x0001
#define ATL1C_INTR_MODRT_ENABLE 0x0002
#define ATL1C_CMB_ENABLE 0x0004
#define ATL1C_SMB_ENABLE 0x0010
#define ATL1C_TXQ_MODE_ENHANCE 0x0020
#define ATL1C_RX_IPV6_CHKSUM 0x0040
#define ATL1C_ASPM_L0S_SUPPORT 0x0080
#define ATL1C_ASPM_L1_SUPPORT 0x0100
#define ATL1C_ASPM_CTRL_MON 0x0200
#define ATL1C_HIB_DISABLE 0x0400
#define ATL1C_LINK_CAP_1000M 0x0800
#define ATL1C_FPGA_VERSION 0x8000
u16 cmb_tpd;
u16 cmb_rrd;
u16 cmb_rx_timer; /* 2us resolution */
u16 cmb_tx_timer;
u32 smb_timer;
u16 rrd_thresh; /* Threshold of number of RRD produced to trigger
interrupt request */
u16 tpd_thresh;
u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */
u8 rfd_burst;
enum atl1c_rss_type rss_type;
enum atl1c_rss_mode rss_mode;
u8 rss_hash_bits;
u32 base_cpu;
u32 indirect_tab;
u8 mac_addr[ETH_ALEN];
u8 perm_mac_addr[ETH_ALEN];
bool phy_configured;
bool re_autoneg;
bool emi_ca;
};
/*
* atl1c_ring_header represents a single, contiguous block of DMA space
* mapped for the three descriptor rings (tpd, rfd, rrd) and the two
* message blocks (cmb, smb) described below
*/
struct atl1c_ring_header {
void *desc; /* virtual address */
dma_addr_t dma; /* physical address*/
unsigned int size; /* length in bytes */
};
/*
* atl1c_buffer is wrapper around a pointer to a socket buffer
* so a DMA handle can be stored along with the skb
*/
struct atl1c_buffer {
struct sk_buff *skb; /* socket buffer */
u16 length; /* rx buffer length */
u16 state; /* state of buffer */
#define ATL1_BUFFER_FREE 0
#define ATL1_BUFFER_BUSY 1
dma_addr_t dma;
};
/* transimit packet descriptor (tpd) ring */
struct atl1c_tpd_ring {
void *desc; /* descriptor ring virtual address */
dma_addr_t dma; /* descriptor ring physical address */
u16 size; /* descriptor ring length in bytes */
u16 count; /* number of descriptors in the ring */
u16 next_to_use; /* this is protectd by adapter->tx_lock */
atomic_t next_to_clean;
struct atl1c_buffer *buffer_info;
};
/* receive free descriptor (rfd) ring */
struct atl1c_rfd_ring {
void *desc; /* descriptor ring virtual address */
dma_addr_t dma; /* descriptor ring physical address */
u16 size; /* descriptor ring length in bytes */
u16 count; /* number of descriptors in the ring */
u16 next_to_use;
u16 next_to_clean;
struct atl1c_buffer *buffer_info;
};
/* receive return desciptor (rrd) ring */
struct atl1c_rrd_ring {
void *desc; /* descriptor ring virtual address */
dma_addr_t dma; /* descriptor ring physical address */
u16 size; /* descriptor ring length in bytes */
u16 count; /* number of descriptors in the ring */
u16 next_to_use;
u16 next_to_clean;
};
struct atl1c_cmb {
void *cmb;
dma_addr_t dma;
};
struct atl1c_smb {
void *smb;
dma_addr_t dma;
};
/* board specific private data structure */
struct atl1c_adapter {
struct net_device *netdev;
struct pci_dev *pdev;
struct vlan_group *vlgrp;
struct napi_struct napi;
struct atl1c_hw hw;
struct atl1c_hw_stats hw_stats;
struct net_device_stats net_stats;
struct mii_if_info mii; /* MII interface info */
u16 rx_buffer_len;
unsigned long flags;
#define __AT_TESTING 0x0001
#define __AT_RESETTING 0x0002
#define __AT_DOWN 0x0003
u32 msg_enable;
bool have_msi;
u32 wol;
u16 link_speed;
u16 link_duplex;
spinlock_t mdio_lock;
spinlock_t tx_lock;
atomic_t irq_sem;
struct work_struct reset_task;
struct work_struct link_chg_task;
struct timer_list watchdog_timer;
struct timer_list phy_config_timer;
/* All Descriptor memory */
struct atl1c_ring_header ring_header;
struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE];
struct atl1c_rfd_ring rfd_ring[AT_MAX_RECEIVE_QUEUE];
struct atl1c_rrd_ring rrd_ring[AT_MAX_RECEIVE_QUEUE];
struct atl1c_cmb cmb;
struct atl1c_smb smb;
int num_rx_queues;
u32 bd_number; /* board number;*/
};
#define AT_WRITE_REG(a, reg, value) ( \
writel((value), ((a)->hw_addr + reg)))
#define AT_WRITE_FLUSH(a) (\
readl((a)->hw_addr))
#define AT_READ_REG(a, reg, pdata) do { \
if (unlikely((a)->hibernate)) { \
readl((a)->hw_addr + reg); \
*(u32 *)pdata = readl((a)->hw_addr + reg); \
} else { \
*(u32 *)pdata = readl((a)->hw_addr + reg); \
} \
} while (0)
#define AT_WRITE_REGB(a, reg, value) (\
writeb((value), ((a)->hw_addr + reg)))
#define AT_READ_REGB(a, reg) (\
readb((a)->hw_addr + reg))
#define AT_WRITE_REGW(a, reg, value) (\
writew((value), ((a)->hw_addr + reg)))
#define AT_READ_REGW(a, reg) (\
readw((a)->hw_addr + reg))
#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
#define AT_READ_REG_ARRAY(a, reg, offset) ( \
readl(((a)->hw_addr + reg) + ((offset) << 2)))
extern char atl1c_driver_name[];
extern char atl1c_driver_version[];
extern int atl1c_up(struct atl1c_adapter *adapter);
extern void atl1c_down(struct atl1c_adapter *adapter);
extern void atl1c_reinit_locked(struct atl1c_adapter *adapter);
extern s32 atl1c_reset_hw(struct atl1c_hw *hw);
extern void atl1c_set_ethtool_ops(struct net_device *netdev);
#endif /* _ATL1C_H_ */

317
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/*
* Copyright(c) 2009 - 2009 Atheros Corporation. All rights reserved.
*
* Derived from Intel e1000 driver
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
*/
#include <linux/netdevice.h>
#include <linux/ethtool.h>
#include "atl1c.h"
static int atl1c_get_settings(struct net_device *netdev,
struct ethtool_cmd *ecmd)
{
struct atl1c_adapter *adapter = netdev_priv(netdev);
struct atl1c_hw *hw = &adapter->hw;
ecmd->supported = (SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full |
SUPPORTED_Autoneg |
SUPPORTED_TP);
if (hw->ctrl_flags & ATL1C_LINK_CAP_1000M)
ecmd->supported |= SUPPORTED_1000baseT_Full;
ecmd->advertising = ADVERTISED_TP;
ecmd->advertising |= hw->autoneg_advertised;
ecmd->port = PORT_TP;
ecmd->phy_address = 0;
ecmd->transceiver = XCVR_INTERNAL;
if (adapter->link_speed != SPEED_0) {
ecmd->speed = adapter->link_speed;
if (adapter->link_duplex == FULL_DUPLEX)
ecmd->duplex = DUPLEX_FULL;
else
ecmd->duplex = DUPLEX_HALF;
} else {
ecmd->speed = -1;
ecmd->duplex = -1;
}
ecmd->autoneg = AUTONEG_ENABLE;
return 0;
}
static int atl1c_set_settings(struct net_device *netdev,
struct ethtool_cmd *ecmd)
{
struct atl1c_adapter *adapter = netdev_priv(netdev);
struct atl1c_hw *hw = &adapter->hw;
u16 autoneg_advertised;
while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
msleep(1);
if (ecmd->autoneg == AUTONEG_ENABLE) {
autoneg_advertised = ADVERTISED_Autoneg;
} else {
if (ecmd->speed == SPEED_1000) {
if (ecmd->duplex != DUPLEX_FULL) {
if (netif_msg_link(adapter))
dev_warn(&adapter->pdev->dev,
"1000M half is invalid\n");
clear_bit(__AT_RESETTING, &adapter->flags);
return -EINVAL;
}
autoneg_advertised = ADVERTISED_1000baseT_Full;
} else if (ecmd->speed == SPEED_100) {
if (ecmd->duplex == DUPLEX_FULL)
autoneg_advertised = ADVERTISED_100baseT_Full;
else
autoneg_advertised = ADVERTISED_100baseT_Half;
} else {
if (ecmd->duplex == DUPLEX_FULL)
autoneg_advertised = ADVERTISED_10baseT_Full;
else
autoneg_advertised = ADVERTISED_10baseT_Half;
}
}
if (hw->autoneg_advertised != autoneg_advertised) {
hw->autoneg_advertised = autoneg_advertised;
if (atl1c_restart_autoneg(hw) != 0) {
if (netif_msg_link(adapter))
dev_warn(&adapter->pdev->dev,
"ethtool speed/duplex setting failed\n");
clear_bit(__AT_RESETTING, &adapter->flags);
return -EINVAL;
}
}
clear_bit(__AT_RESETTING, &adapter->flags);
return 0;
}
static u32 atl1c_get_tx_csum(struct net_device *netdev)
{
return (netdev->features & NETIF_F_HW_CSUM) != 0;
}
static u32 atl1c_get_msglevel(struct net_device *netdev)
{
struct atl1c_adapter *adapter = netdev_priv(netdev);
return adapter->msg_enable;
}
static void atl1c_set_msglevel(struct net_device *netdev, u32 data)
{
struct atl1c_adapter *adapter = netdev_priv(netdev);
adapter->msg_enable = data;
}
static int atl1c_get_regs_len(struct net_device *netdev)
{
return AT_REGS_LEN;
}
static void atl1c_get_regs(struct net_device *netdev,
struct ethtool_regs *regs, void *p)
{
struct atl1c_adapter *adapter = netdev_priv(netdev);
struct atl1c_hw *hw = &adapter->hw;
u32 *regs_buff = p;
u16 phy_data;
memset(p, 0, AT_REGS_LEN);
regs->version = 0;
AT_READ_REG(hw, REG_VPD_CAP, p++);
AT_READ_REG(hw, REG_PM_CTRL, p++);
AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL, p++);
AT_READ_REG(hw, REG_TWSI_CTRL, p++);
AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL, p++);
AT_READ_REG(hw, REG_MASTER_CTRL, p++);
AT_READ_REG(hw, REG_MANUAL_TIMER_INIT, p++);
AT_READ_REG(hw, REG_IRQ_MODRT_TIMER_INIT, p++);
AT_READ_REG(hw, REG_GPHY_CTRL, p++);
AT_READ_REG(hw, REG_LINK_CTRL, p++);
AT_READ_REG(hw, REG_IDLE_STATUS, p++);
AT_READ_REG(hw, REG_MDIO_CTRL, p++);
AT_READ_REG(hw, REG_SERDES_LOCK, p++);
AT_READ_REG(hw, REG_MAC_CTRL, p++);
AT_READ_REG(hw, REG_MAC_IPG_IFG, p++);
AT_READ_REG(hw, REG_MAC_STA_ADDR, p++);
AT_READ_REG(hw, REG_MAC_STA_ADDR+4, p++);
AT_READ_REG(hw, REG_RX_HASH_TABLE, p++);
AT_READ_REG(hw, REG_RX_HASH_TABLE+4, p++);
AT_READ_REG(hw, REG_RXQ_CTRL, p++);
AT_READ_REG(hw, REG_TXQ_CTRL, p++);
AT_READ_REG(hw, REG_MTU, p++);
AT_READ_REG(hw, REG_WOL_CTRL, p++);
atl1c_read_phy_reg(hw, MII_BMCR, &phy_data);
regs_buff[73] = (u32) phy_data;
atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
regs_buff[74] = (u32) phy_data;
}
static int atl1c_get_eeprom_len(struct net_device *netdev)
{
struct atl1c_adapter *adapter = netdev_priv(netdev);
if (atl1c_check_eeprom_exist(&adapter->hw))
return AT_EEPROM_LEN;
else
return 0;
}
static int atl1c_get_eeprom(struct net_device *netdev,
struct ethtool_eeprom *eeprom, u8 *bytes)
{
struct atl1c_adapter *adapter = netdev_priv(netdev);
struct atl1c_hw *hw = &adapter->hw;
u32 *eeprom_buff;
int first_dword, last_dword;
int ret_val = 0;
int i;
if (eeprom->len == 0)
return -EINVAL;
if (!atl1c_check_eeprom_exist(hw)) /* not exist */
return -EINVAL;
eeprom->magic = adapter->pdev->vendor |
(adapter->pdev->device << 16);
first_dword = eeprom->offset >> 2;
last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
eeprom_buff = kmalloc(sizeof(u32) *
(last_dword - first_dword + 1), GFP_KERNEL);
if (eeprom_buff == NULL)
return -ENOMEM;
for (i = first_dword; i < last_dword; i++) {
if (!atl1c_read_eeprom(hw, i * 4, &(eeprom_buff[i-first_dword]))) {
kfree(eeprom_buff);
return -EIO;
}
}
memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
eeprom->len);
kfree(eeprom_buff);
return ret_val;
return 0;
}
static void atl1c_get_drvinfo(struct net_device *netdev,
struct ethtool_drvinfo *drvinfo)
{
struct atl1c_adapter *adapter = netdev_priv(netdev);
strncpy(drvinfo->driver, atl1c_driver_name, sizeof(drvinfo->driver));
strncpy(drvinfo->version, atl1c_driver_version,
sizeof(drvinfo->version));
strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
sizeof(drvinfo->bus_info));
drvinfo->n_stats = 0;
drvinfo->testinfo_len = 0;
drvinfo->regdump_len = atl1c_get_regs_len(netdev);
drvinfo->eedump_len = atl1c_get_eeprom_len(netdev);
}
static void atl1c_get_wol(struct net_device *netdev,
struct ethtool_wolinfo *wol)
{
struct atl1c_adapter *adapter = netdev_priv(netdev);
wol->supported = WAKE_MAGIC | WAKE_PHY;
wol->wolopts = 0;
if (adapter->wol & AT_WUFC_EX)
wol->wolopts |= WAKE_UCAST;
if (adapter->wol & AT_WUFC_MC)
wol->wolopts |= WAKE_MCAST;
if (adapter->wol & AT_WUFC_BC)
wol->wolopts |= WAKE_BCAST;
if (adapter->wol & AT_WUFC_MAG)
wol->wolopts |= WAKE_MAGIC;
if (adapter->wol & AT_WUFC_LNKC)
wol->wolopts |= WAKE_PHY;
return;
}
static int atl1c_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
{
struct atl1c_adapter *adapter = netdev_priv(netdev);
if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE |
WAKE_MCAST | WAKE_BCAST | WAKE_MCAST))
return -EOPNOTSUPP;
/* these settings will always override what we currently have */
adapter->wol = 0;
if (wol->wolopts & WAKE_MAGIC)
adapter->wol |= AT_WUFC_MAG;
if (wol->wolopts & WAKE_PHY)
adapter->wol |= AT_WUFC_LNKC;
return 0;
}
static int atl1c_nway_reset(struct net_device *netdev)
{
struct atl1c_adapter *adapter = netdev_priv(netdev);
if (netif_running(netdev))
atl1c_reinit_locked(adapter);
return 0;
}
static struct ethtool_ops atl1c_ethtool_ops = {
.get_settings = atl1c_get_settings,
.set_settings = atl1c_set_settings,
.get_drvinfo = atl1c_get_drvinfo,
.get_regs_len = atl1c_get_regs_len,
.get_regs = atl1c_get_regs,
.get_wol = atl1c_get_wol,
.set_wol = atl1c_set_wol,
.get_msglevel = atl1c_get_msglevel,
.set_msglevel = atl1c_set_msglevel,
.nway_reset = atl1c_nway_reset,
.get_link = ethtool_op_get_link,
.get_eeprom_len = atl1c_get_eeprom_len,
.get_eeprom = atl1c_get_eeprom,
.get_tx_csum = atl1c_get_tx_csum,
.get_sg = ethtool_op_get_sg,
.set_sg = ethtool_op_set_sg,
};
void atl1c_set_ethtool_ops(struct net_device *netdev)
{
SET_ETHTOOL_OPS(netdev, &atl1c_ethtool_ops);
}

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/*
* Copyright(c) 2007 Atheros Corporation. All rights reserved.
*
* Derived from Intel e1000 driver
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/mii.h>
#include <linux/crc32.h>
#include "atl1c.h"
/*
* check_eeprom_exist
* return 1 if eeprom exist
*/
int atl1c_check_eeprom_exist(struct atl1c_hw *hw)
{
u32 data;
AT_READ_REG(hw, REG_TWSI_DEBUG, &data);
if (data & TWSI_DEBUG_DEV_EXIST)
return 1;
return 0;
}
void atl1c_hw_set_mac_addr(struct atl1c_hw *hw)
{
u32 value;
/*
* 00-0B-6A-F6-00-DC
* 0: 6AF600DC 1: 000B
* low dword
*/
value = (((u32)hw->mac_addr[2]) << 24) |
(((u32)hw->mac_addr[3]) << 16) |
(((u32)hw->mac_addr[4]) << 8) |
(((u32)hw->mac_addr[5])) ;
AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
/* hight dword */
value = (((u32)hw->mac_addr[0]) << 8) |
(((u32)hw->mac_addr[1])) ;
AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
}
/*
* atl1c_get_permanent_address
* return 0 if get valid mac address,
*/
static int atl1c_get_permanent_address(struct atl1c_hw *hw)
{
u32 addr[2];
u32 i;
u32 otp_ctrl_data;
u32 twsi_ctrl_data;
u8 eth_addr[ETH_ALEN];
/* init */
addr[0] = addr[1] = 0;
AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
if (atl1c_check_eeprom_exist(hw)) {
/* Enable OTP CLK */
if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) {
otp_ctrl_data |= OTP_CTRL_CLK_EN;
AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
AT_WRITE_FLUSH(hw);
msleep(1);
}
AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
msleep(10);
AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
break;
}
if (i >= AT_TWSI_EEPROM_TIMEOUT)
return -1;
}
/* Disable OTP_CLK */
if (otp_ctrl_data & OTP_CTRL_CLK_EN) {
otp_ctrl_data &= ~OTP_CTRL_CLK_EN;
AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
AT_WRITE_FLUSH(hw);
msleep(1);
}
/* maybe MAC-address is from BIOS */
AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]);
AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]);
*(u32 *) &eth_addr[2] = swab32(addr[0]);
*(u16 *) &eth_addr[0] = swab16(*(u16 *)&addr[1]);
if (is_valid_ether_addr(eth_addr)) {
memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
return 0;
}
return -1;
}
bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value)
{
int i;
int ret = false;
u32 otp_ctrl_data;
u32 control;
u32 data;
if (offset & 3)
return ret; /* address do not align */
AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
if (!(otp_ctrl_data & OTP_CTRL_CLK_EN))
AT_WRITE_REG(hw, REG_OTP_CTRL,
(otp_ctrl_data | OTP_CTRL_CLK_EN));
AT_WRITE_REG(hw, REG_EEPROM_DATA_LO, 0);
control = (offset & EEPROM_CTRL_ADDR_MASK) << EEPROM_CTRL_ADDR_SHIFT;
AT_WRITE_REG(hw, REG_EEPROM_CTRL, control);
for (i = 0; i < 10; i++) {
udelay(100);
AT_READ_REG(hw, REG_EEPROM_CTRL, &control);
if (control & EEPROM_CTRL_RW)
break;
}
if (control & EEPROM_CTRL_RW) {
AT_READ_REG(hw, REG_EEPROM_CTRL, &data);
AT_READ_REG(hw, REG_EEPROM_DATA_LO, p_value);
data = data & 0xFFFF;
*p_value = swab32((data << 16) | (*p_value >> 16));
ret = true;
}
if (!(otp_ctrl_data & OTP_CTRL_CLK_EN))
AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
return ret;
}
/*
* Reads the adapter's MAC address from the EEPROM
*
* hw - Struct containing variables accessed by shared code
*/
int atl1c_read_mac_addr(struct atl1c_hw *hw)
{
int err = 0;
err = atl1c_get_permanent_address(hw);
if (err)
random_ether_addr(hw->perm_mac_addr);
memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
return 0;
}
/*
* atl1c_hash_mc_addr
* purpose
* set hash value for a multicast address
* hash calcu processing :
* 1. calcu 32bit CRC for multicast address
* 2. reverse crc with MSB to LSB
*/
u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr)
{
u32 crc32;
u32 value = 0;
int i;
crc32 = ether_crc_le(6, mc_addr);
for (i = 0; i < 32; i++)
value |= (((crc32 >> i) & 1) << (31 - i));
return value;
}
/*
* Sets the bit in the multicast table corresponding to the hash value.
* hw - Struct containing variables accessed by shared code
* hash_value - Multicast address hash value
*/
void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value)
{
u32 hash_bit, hash_reg;
u32 mta;
/*
* The HASH Table is a register array of 2 32-bit registers.
* It is treated like an array of 64 bits. We want to set
* bit BitArray[hash_value]. So we figure out what register
* the bit is in, read it, OR in the new bit, then write
* back the new value. The register is determined by the
* upper bit of the hash value and the bit within that
* register are determined by the lower 5 bits of the value.
*/
hash_reg = (hash_value >> 31) & 0x1;
hash_bit = (hash_value >> 26) & 0x1F;
mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
mta |= (1 << hash_bit);
AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
}
/*
* Reads the value from a PHY register
* hw - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to read
*/
int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
{
u32 val;
int i;
val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
for (i = 0; i < MDIO_WAIT_TIMES; i++) {
udelay(2);
AT_READ_REG(hw, REG_MDIO_CTRL, &val);
if (!(val & (MDIO_START | MDIO_BUSY)))
break;
}
if (!(val & (MDIO_START | MDIO_BUSY))) {
*phy_data = (u16)val;
return 0;
}
return -1;
}
/*
* Writes a value to a PHY register
* hw - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to write
* data - data to write to the PHY
*/
int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data)
{
int i;
u32 val;
val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
(reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
MDIO_SUP_PREAMBLE | MDIO_START |
MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
for (i = 0; i < MDIO_WAIT_TIMES; i++) {
udelay(2);
AT_READ_REG(hw, REG_MDIO_CTRL, &val);
if (!(val & (MDIO_START | MDIO_BUSY)))
break;
}
if (!(val & (MDIO_START | MDIO_BUSY)))
return 0;
return -1;
}
/*
* Configures PHY autoneg and flow control advertisement settings
*
* hw - Struct containing variables accessed by shared code
*/
static int atl1c_phy_setup_adv(struct atl1c_hw *hw)
{
u16 mii_adv_data = ADVERTISE_DEFAULT_CAP & ~ADVERTISE_SPEED_MASK;
u16 mii_giga_ctrl_data = GIGA_CR_1000T_DEFAULT_CAP &
~GIGA_CR_1000T_SPEED_MASK;
if (hw->autoneg_advertised & ADVERTISED_10baseT_Half)
mii_adv_data |= ADVERTISE_10HALF;
if (hw->autoneg_advertised & ADVERTISED_10baseT_Full)
mii_adv_data |= ADVERTISE_10FULL;
if (hw->autoneg_advertised & ADVERTISED_100baseT_Half)
mii_adv_data |= ADVERTISE_100HALF;
if (hw->autoneg_advertised & ADVERTISED_100baseT_Full)
mii_adv_data |= ADVERTISE_100FULL;
if (hw->autoneg_advertised & ADVERTISED_Autoneg)
mii_adv_data |= ADVERTISE_10HALF | ADVERTISE_10FULL |
ADVERTISE_100HALF | ADVERTISE_100FULL;
if (hw->ctrl_flags & ATL1C_LINK_CAP_1000M) {
if (hw->autoneg_advertised & ADVERTISED_1000baseT_Half)
mii_giga_ctrl_data |= ADVERTISE_1000HALF;
if (hw->autoneg_advertised & ADVERTISED_1000baseT_Full)
mii_giga_ctrl_data |= ADVERTISE_1000FULL;
if (hw->autoneg_advertised & ADVERTISED_Autoneg)
mii_giga_ctrl_data |= ADVERTISE_1000HALF |
ADVERTISE_1000FULL;
}
if (atl1c_write_phy_reg(hw, MII_ADVERTISE, mii_adv_data) != 0 ||
atl1c_write_phy_reg(hw, MII_GIGA_CR, mii_giga_ctrl_data) != 0)
return -1;
return 0;
}
void atl1c_phy_disable(struct atl1c_hw *hw)
{
AT_WRITE_REGW(hw, REG_GPHY_CTRL,
GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
}
static void atl1c_phy_magic_data(struct atl1c_hw *hw)
{
u16 data;
data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
((1 & ANA_INTERVAL_SEL_TIMER_MASK) <<
ANA_INTERVAL_SEL_TIMER_SHIFT);
atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_18);
atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
data = (2 & ANA_SERDES_CDR_BW_MASK) | ANA_MS_PAD_DBG |
ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
ANA_SERDES_EN_LCKDT;
atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_5);
atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
data = (44 & ANA_LONG_CABLE_TH_100_MASK) |
((33 & ANA_SHORT_CABLE_TH_100_MASK) <<
ANA_SHORT_CABLE_TH_100_SHIFT) | ANA_BP_BAD_LINK_ACCUM |
ANA_BP_SMALL_BW;
atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_54);
atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
data = (11 & ANA_IECHO_ADJ_MASK) | ((11 & ANA_IECHO_ADJ_MASK) <<
ANA_IECHO_ADJ_2_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
ANA_IECHO_ADJ_1_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
ANA_IECHO_ADJ_0_SHIFT);
atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_4);
atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
data = ANA_RESTART_CAL | ((7 & ANA_MANUL_SWICH_ON_MASK) <<
ANA_MANUL_SWICH_ON_SHIFT) | ANA_MAN_ENABLE |
ANA_SEL_HSP | ANA_EN_HB | ANA_OEN_125M;
atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_0);
atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
if (hw->ctrl_flags & ATL1C_HIB_DISABLE) {
atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_41);
if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
return;
data &= ~ANA_TOP_PS_EN;
atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_11);
if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
return;
data &= ~ANA_PS_HIB_EN;
atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
}
}
int atl1c_phy_reset(struct atl1c_hw *hw)
{
struct atl1c_adapter *adapter = hw->adapter;
struct pci_dev *pdev = adapter->pdev;
u32 phy_ctrl_data = GPHY_CTRL_DEFAULT;
u32 mii_ier_data = IER_LINK_UP | IER_LINK_DOWN;
int err;
if (hw->ctrl_flags & ATL1C_HIB_DISABLE)
phy_ctrl_data &= ~GPHY_CTRL_HIB_EN;
AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
AT_WRITE_FLUSH(hw);
msleep(40);
phy_ctrl_data |= GPHY_CTRL_EXT_RESET;
AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
AT_WRITE_FLUSH(hw);
msleep(10);
/*Enable PHY LinkChange Interrupt */
err = atl1c_write_phy_reg(hw, MII_IER, mii_ier_data);
if (err) {
if (netif_msg_hw(adapter))
dev_err(&pdev->dev,
"Error enable PHY linkChange Interrupt\n");
return err;
}
if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION))
atl1c_phy_magic_data(hw);
return 0;
}
int atl1c_phy_init(struct atl1c_hw *hw)
{
struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
struct pci_dev *pdev = adapter->pdev;
int ret_val;
u16 mii_bmcr_data = BMCR_RESET;
u16 phy_id1, phy_id2;
if ((atl1c_read_phy_reg(hw, MII_PHYSID1, &phy_id1) != 0) ||
(atl1c_read_phy_reg(hw, MII_PHYSID2, &phy_id2) != 0)) {
if (netif_msg_link(adapter))
dev_err(&pdev->dev, "Error get phy ID\n");
return -1;
}
switch (hw->media_type) {
case MEDIA_TYPE_AUTO_SENSOR:
ret_val = atl1c_phy_setup_adv(hw);
if (ret_val) {
if (netif_msg_link(adapter))
dev_err(&pdev->dev,
"Error Setting up Auto-Negotiation\n");
return ret_val;
}
mii_bmcr_data |= BMCR_AUTO_NEG_EN | BMCR_RESTART_AUTO_NEG;
break;
case MEDIA_TYPE_100M_FULL:
mii_bmcr_data |= BMCR_SPEED_100 | BMCR_FULL_DUPLEX;
break;
case MEDIA_TYPE_100M_HALF:
mii_bmcr_data |= BMCR_SPEED_100;
break;
case MEDIA_TYPE_10M_FULL:
mii_bmcr_data |= BMCR_SPEED_10 | BMCR_FULL_DUPLEX;
break;
case MEDIA_TYPE_10M_HALF:
mii_bmcr_data |= BMCR_SPEED_10;
break;
default:
if (netif_msg_link(adapter))
dev_err(&pdev->dev, "Wrong Media type %d\n",
hw->media_type);
return -1;
break;
}
ret_val = atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
if (ret_val)
return ret_val;
hw->phy_configured = true;
return 0;
}
/*
* Detects the current speed and duplex settings of the hardware.
*
* hw - Struct containing variables accessed by shared code
* speed - Speed of the connection
* duplex - Duplex setting of the connection
*/
int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex)
{
int err;
u16 phy_data;
/* Read PHY Specific Status Register (17) */
err = atl1c_read_phy_reg(hw, MII_GIGA_PSSR, &phy_data);
if (err)
return err;
if (!(phy_data & GIGA_PSSR_SPD_DPLX_RESOLVED))
return -1;
switch (phy_data & GIGA_PSSR_SPEED) {
case GIGA_PSSR_1000MBS:
*speed = SPEED_1000;
break;
case GIGA_PSSR_100MBS:
*speed = SPEED_100;
break;
case GIGA_PSSR_10MBS:
*speed = SPEED_10;
break;
default:
return -1;
break;
}
if (phy_data & GIGA_PSSR_DPLX)
*duplex = FULL_DUPLEX;
else
*duplex = HALF_DUPLEX;
return 0;
}
int atl1c_restart_autoneg(struct atl1c_hw *hw)
{
int err = 0;
u16 mii_bmcr_data = BMCR_RESET;
err = atl1c_phy_setup_adv(hw);
if (err)
return err;
mii_bmcr_data |= BMCR_AUTO_NEG_EN | BMCR_RESTART_AUTO_NEG;
return atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
}

859
drivers/net/atl1c/atl1c_hw.h Normal file
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@ -0,0 +1,859 @@
/*
* Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
*
* Derived from Intel e1000 driver
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _ATL1C_HW_H_
#define _ATL1C_HW_H_
#include <linux/types.h>
#include <linux/mii.h>
struct atl1c_adapter;
struct atl1c_hw;
/* function prototype */
void atl1c_phy_disable(struct atl1c_hw *hw);
void atl1c_hw_set_mac_addr(struct atl1c_hw *hw);
int atl1c_phy_reset(struct atl1c_hw *hw);
int atl1c_read_mac_addr(struct atl1c_hw *hw);
int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex);
u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr);
void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value);
int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data);
bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value);
int atl1c_phy_init(struct atl1c_hw *hw);
int atl1c_check_eeprom_exist(struct atl1c_hw *hw);
int atl1c_restart_autoneg(struct atl1c_hw *hw);
/* register definition */
#define REG_DEVICE_CAP 0x5C
#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
#define REG_DEVICE_CTRL 0x60
#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
#define REG_LINK_CTRL 0x68
#define LINK_CTRL_L0S_EN 0x01
#define LINK_CTRL_L1_EN 0x02
#define REG_VPD_CAP 0x6C
#define VPD_CAP_ID_MASK 0xff
#define VPD_CAP_ID_SHIFT 0
#define VPD_CAP_NEXT_PTR_MASK 0xFF
#define VPD_CAP_NEXT_PTR_SHIFT 8
#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
#define VPD_CAP_VPD_ADDR_SHIFT 16
#define VPD_CAP_VPD_FLAG 0x80000000
#define REG_VPD_DATA 0x70
#define REG_PCIE_UC_SEVERITY 0x10C
#define PCIE_UC_SERVRITY_TRN 0x00000001
#define PCIE_UC_SERVRITY_DLP 0x00000010
#define PCIE_UC_SERVRITY_PSN_TLP 0x00001000
#define PCIE_UC_SERVRITY_FCP 0x00002000
#define PCIE_UC_SERVRITY_CPL_TO 0x00004000
#define PCIE_UC_SERVRITY_CA 0x00008000
#define PCIE_UC_SERVRITY_UC 0x00010000
#define PCIE_UC_SERVRITY_ROV 0x00020000
#define PCIE_UC_SERVRITY_MLFP 0x00040000
#define PCIE_UC_SERVRITY_ECRC 0x00080000
#define PCIE_UC_SERVRITY_UR 0x00100000
#define REG_DEV_SERIALNUM_CTRL 0x200
#define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */
#define REG_DEV_MAC_SEL_SHIFT 0
#define REG_DEV_SERIAL_NUM_EN_MASK 0x1
#define REG_DEV_SERIAL_NUM_EN_SHIFT 1
#define REG_TWSI_CTRL 0x218
#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
#define TWSI_CTRL_LD_OFFSET_SHIFT 0
#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
#define TWSI_CTRL_SW_LDSTART 0x800
#define TWSI_CTRL_HW_LDSTART 0x1000
#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
#define TWSI_CTRL_LD_EXIST 0x400000
#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
#define TWSI_CTRL_FREQ_SEL_100K 0
#define TWSI_CTRL_FREQ_SEL_200K 1
#define TWSI_CTRL_FREQ_SEL_300K 2
#define TWSI_CTRL_FREQ_SEL_400K 3
#define TWSI_CTRL_SMB_SLV_ADDR
#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
#define REG_PCIE_DEV_MISC_CTRL 0x21C
#define PCIE_DEV_MISC_EXT_PIPE 0x2
#define PCIE_DEV_MISC_RETRY_BUFDIS 0x1
#define PCIE_DEV_MISC_SPIROM_EXIST 0x4
#define PCIE_DEV_MISC_SERDES_ENDIAN 0x8
#define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10
#define REG_PCIE_PHYMISC 0x1000
#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
#define REG_TWSI_DEBUG 0x1108
#define TWSI_DEBUG_DEV_EXIST 0x20000000
#define REG_EEPROM_CTRL 0x12C0
#define EEPROM_CTRL_DATA_HI_MASK 0xFFFF
#define EEPROM_CTRL_DATA_HI_SHIFT 0
#define EEPROM_CTRL_ADDR_MASK 0x3FF
#define EEPROM_CTRL_ADDR_SHIFT 16
#define EEPROM_CTRL_ACK 0x40000000
#define EEPROM_CTRL_RW 0x80000000
#define REG_EEPROM_DATA_LO 0x12C4
#define REG_OTP_CTRL 0x12F0
#define OTP_CTRL_CLK_EN 0x0002
#define REG_PM_CTRL 0x12F8
#define PM_CTRL_SDES_EN 0x00000001
#define PM_CTRL_RBER_EN 0x00000002
#define PM_CTRL_CLK_REQ_EN 0x00000004
#define PM_CTRL_ASPM_L1_EN 0x00000008
#define PM_CTRL_SERDES_L1_EN 0x00000010
#define PM_CTRL_SERDES_PLL_L1_EN 0x00000020
#define PM_CTRL_SERDES_PD_EX_L1 0x00000040
#define PM_CTRL_SERDES_BUDS_RX_L1_EN 0x00000080
#define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xF
#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8
#define PM_CTRL_ASPM_L0S_EN 0x00001000
#define PM_CTRL_CLK_SWH_L1 0x00002000
#define PM_CTRL_CLK_PWM_VER1_1 0x00004000
#define PM_CTRL_PCIE_RECV 0x00008000
#define PM_CTRL_L1_ENTRY_TIMER_MASK 0xF
#define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16
#define PM_CTRL_PM_REQ_TIMER_MASK 0xF
#define PM_CTRL_PM_REQ_TIMER_SHIFT 20
#define PM_CTRL_LCKDET_TIMER_MASK 0x3F
#define PM_CTRL_LCKDET_TIMER_SHIFT 24
#define PM_CTRL_MAC_ASPM_CHK 0x40000000
#define PM_CTRL_HOTRST 0x80000000
/* Selene Master Control Register */
#define REG_MASTER_CTRL 0x1400
#define MASTER_CTRL_SOFT_RST 0x1
#define MASTER_CTRL_TEST_MODE_MASK 0x3
#define MASTER_CTRL_TEST_MODE_SHIFT 2
#define MASTER_CTRL_BERT_START 0x10
#define MASTER_CTRL_MTIMER_EN 0x100
#define MASTER_CTRL_MANUAL_INT 0x200
#define MASTER_CTRL_TX_ITIMER_EN 0x400
#define MASTER_CTRL_RX_ITIMER_EN 0x800
#define MASTER_CTRL_CLK_SEL_DIS 0x1000
#define MASTER_CTRL_CLK_SWH_MODE 0x2000
#define MASTER_CTRL_INT_RDCLR 0x4000
#define MASTER_CTRL_REV_NUM_SHIFT 16
#define MASTER_CTRL_REV_NUM_MASK 0xff
#define MASTER_CTRL_DEV_ID_SHIFT 24
#define MASTER_CTRL_DEV_ID_MASK 0x7f
#define MASTER_CTRL_OTP_SEL 0x80000000
/* Timer Initial Value Register */
#define REG_MANUAL_TIMER_INIT 0x1404
/* IRQ ModeratorTimer Initial Value Register */
#define REG_IRQ_MODRT_TIMER_INIT 0x1408
#define IRQ_MODRT_TIMER_MASK 0xffff
#define IRQ_MODRT_TX_TIMER_SHIFT 0
#define IRQ_MODRT_RX_TIMER_SHIFT 16
#define REG_GPHY_CTRL 0x140C
#define GPHY_CTRL_EXT_RESET 0x1
#define GPHY_CTRL_RTL_MODE 0x2
#define GPHY_CTRL_LED_MODE 0x4
#define GPHY_CTRL_ANEG_NOW 0x8
#define GPHY_CTRL_REV_ANEG 0x10
#define GPHY_CTRL_GATE_25M_EN 0x20
#define GPHY_CTRL_LPW_EXIT 0x40
#define GPHY_CTRL_PHY_IDDQ 0x80
#define GPHY_CTRL_PHY_IDDQ_DIS 0x100
#define GPHY_CTRL_GIGA_DIS 0x200
#define GPHY_CTRL_HIB_EN 0x400
#define GPHY_CTRL_HIB_PULSE 0x800
#define GPHY_CTRL_SEL_ANA_RST 0x1000
#define GPHY_CTRL_PHY_PLL_ON 0x2000
#define GPHY_CTRL_PWDOWN_HW 0x4000
#define GPHY_CTRL_PHY_PLL_BYPASS 0x8000
#define GPHY_CTRL_DEFAULT ( \
GPHY_CTRL_SEL_ANA_RST |\
GPHY_CTRL_HIB_PULSE |\
GPHY_CTRL_HIB_EN)
#define GPHY_CTRL_PW_WOL_DIS ( \
GPHY_CTRL_SEL_ANA_RST |\
GPHY_CTRL_HIB_PULSE |\
GPHY_CTRL_HIB_EN |\
GPHY_CTRL_PWDOWN_HW |\
GPHY_CTRL_PHY_IDDQ)
/* Block IDLE Status Register */
#define REG_IDLE_STATUS 0x1410
#define IDLE_STATUS_MASK 0x00FF
#define IDLE_STATUS_RXMAC_NO_IDLE 0x1
#define IDLE_STATUS_TXMAC_NO_IDLE 0x2
#define IDLE_STATUS_RXQ_NO_IDLE 0x4
#define IDLE_STATUS_TXQ_NO_IDLE 0x8
#define IDLE_STATUS_DMAR_NO_IDLE 0x10
#define IDLE_STATUS_DMAW_NO_IDLE 0x20
#define IDLE_STATUS_SMB_NO_IDLE 0x40
#define IDLE_STATUS_CMB_NO_IDLE 0x80
/* MDIO Control Register */
#define REG_MDIO_CTRL 0x1414
#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit
* control data to write to PHY
* MII management register */
#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit
* status data that was read
* from the PHY MII management register */
#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
#define MDIO_REG_ADDR_SHIFT 16
#define MDIO_RW 0x200000 /* 1: read, 0: write */
#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO
* master. And this bit is self
* cleared after one cycle */
#define MDIO_CLK_SEL_SHIFT 24
#define MDIO_CLK_25_4 0
#define MDIO_CLK_25_6 2
#define MDIO_CLK_25_8 3
#define MDIO_CLK_25_10 4
#define MDIO_CLK_25_14 5
#define MDIO_CLK_25_20 6
#define MDIO_CLK_25_28 7
#define MDIO_BUSY 0x8000000
#define MDIO_AP_EN 0x10000000
#define MDIO_WAIT_TIMES 10
/* MII PHY Status Register */
#define REG_PHY_STATUS 0x1418
#define PHY_GENERAL_STATUS_MASK 0xFFFF
#define PHY_STATUS_RECV_ENABLE 0x0001
#define PHY_OE_PWSP_STATUS_MASK 0x07FF
#define PHY_OE_PWSP_STATUS_SHIFT 16
#define PHY_STATUS_LPW_STATE 0x80000000
/* BIST Control and Status Register0 (for the Packet Memory) */
#define REG_BIST0_CTRL 0x141c
#define BIST0_NOW 0x1
#define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is
* un-repairable because
* it has address decoder
* failure or more than 1 cell
* stuck-to-x failure */
#define BIST0_FUSE_FLAG 0x4
/* BIST Control and Status Register1(for the retry buffer of PCI Express) */
#define REG_BIST1_CTRL 0x1420
#define BIST1_NOW 0x1
#define BIST1_SRAM_FAIL 0x2
#define BIST1_FUSE_FLAG 0x4
/* SerDes Lock Detect Control and Status Register */
#define REG_SERDES_LOCK 0x1424
#define SERDES_LOCK_DETECT 0x1 /* SerDes lock detected. This signal
* comes from Analog SerDes */
#define SERDES_LOCK_DETECT_EN 0x2 /* 1: Enable SerDes Lock detect function */
/* MAC Control Register */
#define REG_MAC_CTRL 0x1480
#define MAC_CTRL_TX_EN 0x1
#define MAC_CTRL_RX_EN 0x2
#define MAC_CTRL_TX_FLOW 0x4
#define MAC_CTRL_RX_FLOW 0x8
#define MAC_CTRL_LOOPBACK 0x10
#define MAC_CTRL_DUPLX 0x20
#define MAC_CTRL_ADD_CRC 0x40
#define MAC_CTRL_PAD 0x80
#define MAC_CTRL_LENCHK 0x100
#define MAC_CTRL_HUGE_EN 0x200
#define MAC_CTRL_PRMLEN_SHIFT 10
#define MAC_CTRL_PRMLEN_MASK 0xf
#define MAC_CTRL_RMV_VLAN 0x4000
#define MAC_CTRL_PROMIS_EN 0x8000
#define MAC_CTRL_TX_PAUSE 0x10000
#define MAC_CTRL_SCNT 0x20000
#define MAC_CTRL_SRST_TX 0x40000
#define MAC_CTRL_TX_SIMURST 0x80000
#define MAC_CTRL_SPEED_SHIFT 20
#define MAC_CTRL_SPEED_MASK 0x3
#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
#define MAC_CTRL_TX_HUGE 0x800000
#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
#define MAC_CTRL_MC_ALL_EN 0x2000000
#define MAC_CTRL_BC_EN 0x4000000
#define MAC_CTRL_DBG 0x8000000
#define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000
/* MAC IPG/IFG Control Register */
#define REG_MAC_IPG_IFG 0x1484
#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back
* inter-packet gap. The
* default is 96-bit time */
#define MAC_IPG_IFG_IPGT_MASK 0x7f
#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to
* enforce in between RX frames */
#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
#define MAC_IPG_IFG_IPGR1_MASK 0x7f
#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
#define MAC_IPG_IFG_IPGR2_MASK 0x7f
/* MAC STATION ADDRESS */
#define REG_MAC_STA_ADDR 0x1488
/* Hash table for multicast address */
#define REG_RX_HASH_TABLE 0x1490
/* MAC Half-Duplex Control Register */
#define REG_MAC_HALF_DUPLX_CTRL 0x1498
#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure,
* immediately start the
* transmission after back pressure */
#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */
#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
/* Maximum Frame Length Control Register */
#define REG_MTU 0x149c
/* Wake-On-Lan control register */
#define REG_WOL_CTRL 0x14a0
#define WOL_PATTERN_EN 0x00000001
#define WOL_PATTERN_PME_EN 0x00000002
#define WOL_MAGIC_EN 0x00000004
#define WOL_MAGIC_PME_EN 0x00000008
#define WOL_LINK_CHG_EN 0x00000010
#define WOL_LINK_CHG_PME_EN 0x00000020
#define WOL_PATTERN_ST 0x00000100
#define WOL_MAGIC_ST 0x00000200
#define WOL_LINKCHG_ST 0x00000400
#define WOL_CLK_SWITCH_EN 0x00008000
#define WOL_PT0_EN 0x00010000
#define WOL_PT1_EN 0x00020000
#define WOL_PT2_EN 0x00040000
#define WOL_PT3_EN 0x00080000
#define WOL_PT4_EN 0x00100000
#define WOL_PT5_EN 0x00200000
#define WOL_PT6_EN 0x00400000
/* WOL Length ( 2 DWORD ) */
#define REG_WOL_PATTERN_LEN 0x14a4
#define WOL_PT_LEN_MASK 0x7f
#define WOL_PT0_LEN_SHIFT 0
#define WOL_PT1_LEN_SHIFT 8
#define WOL_PT2_LEN_SHIFT 16
#define WOL_PT3_LEN_SHIFT 24
#define WOL_PT4_LEN_SHIFT 0
#define WOL_PT5_LEN_SHIFT 8
#define WOL_PT6_LEN_SHIFT 16
/* Internal SRAM Partition Register */
#define RFDX_HEAD_ADDR_MASK 0x03FF
#define RFDX_HARD_ADDR_SHIFT 0
#define RFDX_TAIL_ADDR_MASK 0x03FF
#define RFDX_TAIL_ADDR_SHIFT 16
#define REG_SRAM_RFD0_INFO 0x1500
#define REG_SRAM_RFD1_INFO 0x1504
#define REG_SRAM_RFD2_INFO 0x1508
#define REG_SRAM_RFD3_INFO 0x150C
#define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */
#define RFD_NIC_LEN_MASK 0x03FF
#define REG_SRAM_TRD_ADDR 0x1518
#define TPD_HEAD_ADDR_MASK 0x03FF
#define TPD_HEAD_ADDR_SHIFT 0
#define TPD_TAIL_ADDR_MASK 0x03FF
#define TPD_TAIL_ADDR_SHIFT 16
#define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */
#define TPD_NIC_LEN_MASK 0x03FF
#define REG_SRAM_RXF_ADDR 0x1520
#define REG_SRAM_RXF_LEN 0x1524
#define REG_SRAM_TXF_ADDR 0x1528
#define REG_SRAM_TXF_LEN 0x152C
#define REG_SRAM_TCPH_ADDR 0x1530
#define REG_SRAM_PKTH_ADDR 0x1532
/*
* Load Ptr Register
* Software sets this bit after the initialization of the head and tail */
#define REG_LOAD_PTR 0x1534
/*
* addresses of all descriptors, as well as the following descriptor
* control register, which triggers each function block to load the head
* pointer to prepare for the operation. This bit is then self-cleared
* after one cycle.
*/
#define REG_RX_BASE_ADDR_HI 0x1540
#define REG_TX_BASE_ADDR_HI 0x1544
#define REG_SMB_BASE_ADDR_HI 0x1548
#define REG_SMB_BASE_ADDR_LO 0x154C
#define REG_RFD0_HEAD_ADDR_LO 0x1550
#define REG_RFD1_HEAD_ADDR_LO 0x1554
#define REG_RFD2_HEAD_ADDR_LO 0x1558
#define REG_RFD3_HEAD_ADDR_LO 0x155C
#define REG_RFD_RING_SIZE 0x1560
#define RFD_RING_SIZE_MASK 0x0FFF
#define REG_RX_BUF_SIZE 0x1564
#define RX_BUF_SIZE_MASK 0xFFFF
#define REG_RRD0_HEAD_ADDR_LO 0x1568
#define REG_RRD1_HEAD_ADDR_LO 0x156C
#define REG_RRD2_HEAD_ADDR_LO 0x1570
#define REG_RRD3_HEAD_ADDR_LO 0x1574
#define REG_RRD_RING_SIZE 0x1578
#define RRD_RING_SIZE_MASK 0x0FFF
#define REG_HTPD_HEAD_ADDR_LO 0x157C
#define REG_NTPD_HEAD_ADDR_LO 0x1580
#define REG_TPD_RING_SIZE 0x1584
#define TPD_RING_SIZE_MASK 0xFFFF
#define REG_CMB_BASE_ADDR_LO 0x1588
/* RSS about */
#define REG_RSS_KEY0 0x14B0
#define REG_RSS_KEY1 0x14B4
#define REG_RSS_KEY2 0x14B8
#define REG_RSS_KEY3 0x14BC
#define REG_RSS_KEY4 0x14C0
#define REG_RSS_KEY5 0x14C4
#define REG_RSS_KEY6 0x14C8
#define REG_RSS_KEY7 0x14CC
#define REG_RSS_KEY8 0x14D0
#define REG_RSS_KEY9 0x14D4
#define REG_IDT_TABLE0 0x14E0
#define REG_IDT_TABLE1 0x14E4
#define REG_IDT_TABLE2 0x14E8
#define REG_IDT_TABLE3 0x14EC
#define REG_IDT_TABLE4 0x14F0
#define REG_IDT_TABLE5 0x14F4
#define REG_IDT_TABLE6 0x14F8
#define REG_IDT_TABLE7 0x14FC
#define REG_IDT_TABLE REG_IDT_TABLE0
#define REG_RSS_HASH_VALUE 0x15B0
#define REG_RSS_HASH_FLAG 0x15B4
#define REG_BASE_CPU_NUMBER 0x15B8
/* TXQ Control Register */
#define REG_TXQ_CTRL 0x1590
#define TXQ_NUM_TPD_BURST_MASK 0xF
#define TXQ_NUM_TPD_BURST_SHIFT 0
#define TXQ_CTRL_IP_OPTION_EN 0x10
#define TXQ_CTRL_EN 0x20
#define TXQ_CTRL_ENH_MODE 0x40
#define TXQ_CTRL_LS_8023_EN 0x80
#define TXQ_TXF_BURST_NUM_SHIFT 16
#define TXQ_TXF_BURST_NUM_MASK 0xFFFF
/* Jumbo packet Threshold for task offload */
#define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */
#define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF
#define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */
#define TXF_WATER_MARK_MASK 0x0FFF
#define TXF_LOW_WATER_MARK_SHIFT 0
#define TXF_HIGH_WATER_MARK_SHIFT 16
#define TXQ_CTRL_BURST_MODE_EN 0x80000000
#define REG_THRUPUT_MON_CTRL 0x159C
#define THRUPUT_MON_RATE_MASK 0x3
#define THRUPUT_MON_RATE_SHIFT 0
#define THRUPUT_MON_EN 0x80
/* RXQ Control Register */
#define REG_RXQ_CTRL 0x15A0
#define ASPM_THRUPUT_LIMIT_MASK 0x3
#define ASPM_THRUPUT_LIMIT_SHIFT 0
#define ASPM_THRUPUT_LIMIT_NO 0x00
#define ASPM_THRUPUT_LIMIT_1M 0x01
#define ASPM_THRUPUT_LIMIT_10M 0x02
#define ASPM_THRUPUT_LIMIT_100M 0x04
#define RXQ1_CTRL_EN 0x10
#define RXQ2_CTRL_EN 0x20
#define RXQ3_CTRL_EN 0x40
#define IPV6_CHKSUM_CTRL_EN 0x80
#define RSS_HASH_BITS_MASK 0x00FF
#define RSS_HASH_BITS_SHIFT 8
#define RSS_HASH_IPV4 0x10000
#define RSS_HASH_IPV4_TCP 0x20000
#define RSS_HASH_IPV6 0x40000
#define RSS_HASH_IPV6_TCP 0x80000
#define RXQ_RFD_BURST_NUM_MASK 0x003F
#define RXQ_RFD_BURST_NUM_SHIFT 20
#define RSS_MODE_MASK 0x0003
#define RSS_MODE_SHIFT 26
#define RSS_NIP_QUEUE_SEL_MASK 0x1
#define RSS_NIP_QUEUE_SEL_SHIFT 28
#define RRS_HASH_CTRL_EN 0x20000000
#define RX_CUT_THRU_EN 0x40000000
#define RXQ_CTRL_EN 0x80000000
#define REG_RFD_FREE_THRESH 0x15A4
#define RFD_FREE_THRESH_MASK 0x003F
#define RFD_FREE_HI_THRESH_SHIFT 0
#define RFD_FREE_LO_THRESH_SHIFT 6
/* RXF flow control register */
#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
#define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
#define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF
#define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
#define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF
#define REG_RXD_DMA_CTRL 0x15AC
#define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */
#define RXD_DMA_THRESH_SHIFT 0
#define RXD_DMA_DOWN_TIMER_MASK 0xFFFF
#define RXD_DMA_DOWN_TIMER_SHIFT 16
/* DMA Engine Control Register */
#define REG_DMA_CTRL 0x15C0
#define DMA_CTRL_DMAR_IN_ORDER 0x1
#define DMA_CTRL_DMAR_ENH_ORDER 0x2
#define DMA_CTRL_DMAR_OUT_ORDER 0x4
#define DMA_CTRL_RCB_VALUE 0x8
#define DMA_CTRL_DMAR_BURST_LEN_MASK 0x0007
#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
#define DMA_CTRL_DMAW_BURST_LEN_MASK 0x0007
#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
#define DMA_CTRL_DMAR_REQ_PRI 0x400
#define DMA_CTRL_DMAR_DLY_CNT_MASK 0x001F
#define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
#define DMA_CTRL_DMAW_DLY_CNT_MASK 0x000F
#define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
#define DMA_CTRL_CMB_EN 0x100000
#define DMA_CTRL_SMB_EN 0x200000
#define DMA_CTRL_CMB_NOW 0x400000
#define MAC_CTRL_SMB_DIS 0x1000000
#define DMA_CTRL_SMB_NOW 0x80000000
/* CMB/SMB Control Register */
#define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */
#define SMB_STAT_TIMER_MASK 0xFFFFFF
#define REG_CMB_TPD_THRESH 0x15C8
#define CMB_TPD_THRESH_MASK 0xFFFF
#define REG_CMB_TX_TIMER 0x15CC /* 2us resolution */
#define CMB_TX_TIMER_MASK 0xFFFF
/* Mail box */
#define MB_RFDX_PROD_IDX_MASK 0xFFFF
#define REG_MB_RFD0_PROD_IDX 0x15E0
#define REG_MB_RFD1_PROD_IDX 0x15E4
#define REG_MB_RFD2_PROD_IDX 0x15E8
#define REG_MB_RFD3_PROD_IDX 0x15EC
#define MB_PRIO_PROD_IDX_MASK 0xFFFF
#define REG_MB_PRIO_PROD_IDX 0x15F0
#define MB_HTPD_PROD_IDX_SHIFT 0
#define MB_NTPD_PROD_IDX_SHIFT 16
#define MB_PRIO_CONS_IDX_MASK 0xFFFF
#define REG_MB_PRIO_CONS_IDX 0x15F4
#define MB_HTPD_CONS_IDX_SHIFT 0
#define MB_NTPD_CONS_IDX_SHIFT 16
#define REG_MB_RFD01_CONS_IDX 0x15F8
#define MB_RFD0_CONS_IDX_MASK 0x0000FFFF
#define MB_RFD1_CONS_IDX_MASK 0xFFFF0000
#define REG_MB_RFD23_CONS_IDX 0x15FC
#define MB_RFD2_CONS_IDX_MASK 0x0000FFFF
#define MB_RFD3_CONS_IDX_MASK 0xFFFF0000
/* Interrupt Status Register */
#define REG_ISR 0x1600
#define ISR_SMB 0x00000001
#define ISR_TIMER 0x00000002
/*
* Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
* in Table 51 Selene Master Control Register (Offset 0x1400).
*/
#define ISR_MANUAL 0x00000004
#define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */
#define ISR_RFD0_UR 0x00000010 /* RFD0 under run */
#define ISR_RFD1_UR 0x00000020
#define ISR_RFD2_UR 0x00000040
#define ISR_RFD3_UR 0x00000080
#define ISR_TXF_UR 0x00000100
#define ISR_DMAR_TO_RST 0x00000200
#define ISR_DMAW_TO_RST 0x00000400
#define ISR_TX_CREDIT 0x00000800
#define ISR_GPHY 0x00001000
/* GPHY low power state interrupt */
#define ISR_GPHY_LPW 0x00002000
#define ISR_TXQ_TO_RST 0x00004000
#define ISR_TX_PKT 0x00008000
#define ISR_RX_PKT_0 0x00010000
#define ISR_RX_PKT_1 0x00020000
#define ISR_RX_PKT_2 0x00040000
#define ISR_RX_PKT_3 0x00080000
#define ISR_MAC_RX 0x00100000
#define ISR_MAC_TX 0x00200000
#define ISR_UR_DETECTED 0x00400000
#define ISR_FERR_DETECTED 0x00800000
#define ISR_NFERR_DETECTED 0x01000000
#define ISR_CERR_DETECTED 0x02000000
#define ISR_PHY_LINKDOWN 0x04000000
#define ISR_DIS_INT 0x80000000
/* Interrupt Mask Register */
#define REG_IMR 0x1604
#define IMR_NORMAL_MASK (\
ISR_MANUAL |\
ISR_HW_RXF_OV |\
ISR_RFD0_UR |\
ISR_TXF_UR |\
ISR_DMAR_TO_RST |\
ISR_TXQ_TO_RST |\
ISR_DMAW_TO_RST |\
ISR_GPHY |\
ISR_TX_PKT |\
ISR_RX_PKT_0 |\
ISR_GPHY_LPW |\
ISR_PHY_LINKDOWN)
#define ISR_RX_PKT (\
ISR_RX_PKT_0 |\
ISR_RX_PKT_1 |\
ISR_RX_PKT_2 |\
ISR_RX_PKT_3)
#define ISR_OVER (\
ISR_RFD0_UR |\
ISR_RFD1_UR |\
ISR_RFD2_UR |\
ISR_RFD3_UR |\
ISR_HW_RXF_OV |\
ISR_TXF_UR)
#define ISR_ERROR (\
ISR_DMAR_TO_RST |\
ISR_TXQ_TO_RST |\
ISR_DMAW_TO_RST |\
ISR_PHY_LINKDOWN)
#define REG_INT_RETRIG_TIMER 0x1608
#define INT_RETRIG_TIMER_MASK 0xFFFF
#define REG_HDS_CTRL 0x160C
#define HDS_CTRL_EN 0x0001
#define HDS_CTRL_BACKFILLSIZE_SHIFT 8
#define HDS_CTRL_BACKFILLSIZE_MASK 0x0FFF
#define HDS_CTRL_MAX_HDRSIZE_SHIFT 20
#define HDS_CTRL_MAC_HDRSIZE_MASK 0x0FFF
#define REG_MAC_RX_STATUS_BIN 0x1700
#define REG_MAC_RX_STATUS_END 0x175c
#define REG_MAC_TX_STATUS_BIN 0x1760
#define REG_MAC_TX_STATUS_END 0x17c0
/* DEBUG ADDR */
#define REG_DEBUG_DATA0 0x1900
#define REG_DEBUG_DATA1 0x1904
/* PHY Control Register */
#define MII_BMCR 0x00
#define BMCR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define BMCR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
#define BMCR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
#define BMCR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
#define BMCR_ISOLATE 0x0400 /* Isolate PHY from MII */
#define BMCR_POWER_DOWN 0x0800 /* Power down */
#define BMCR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
#define BMCR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define BMCR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
#define BMCR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
#define BMCR_SPEED_MASK 0x2040
#define BMCR_SPEED_1000 0x0040
#define BMCR_SPEED_100 0x2000
#define BMCR_SPEED_10 0x0000
/* PHY Status Register */
#define MII_BMSR 0x01
#define BMMSR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
#define BMSR_JABBER_DETECT 0x0002 /* Jabber Detected */
#define BMSR_LINK_STATUS 0x0004 /* Link Status 1 = link */
#define BMSR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
#define BMSR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
#define BMSR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
#define BMSR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
#define BMSR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
#define BMSR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
#define BMSR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
#define BMSR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
#define BMSR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
#define BMSR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
#define BMMII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
#define BMMII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
#define MII_PHYSID1 0x02
#define MII_PHYSID2 0x03
/* Autoneg Advertisement Register */
#define MII_ADVERTISE 0x04
#define ADVERTISE_SPEED_MASK 0x01E0
#define ADVERTISE_DEFAULT_CAP 0x0DE0
/* 1000BASE-T Control Register */
#define MII_GIGA_CR 0x09
#define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */
#define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
#define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
#define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
#define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
#define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
#define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
#define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
#define GIGA_CR_1000T_SPEED_MASK 0x0300
#define GIGA_CR_1000T_DEFAULT_CAP 0x0300
/* PHY Specific Status Register */
#define MII_GIGA_PSSR 0x11
#define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
#define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
#define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
#define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */
#define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */
#define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
/* PHY Interrupt Enable Register */
#define MII_IER 0x12
#define IER_LINK_UP 0x0400
#define IER_LINK_DOWN 0x0800
/* PHY Interrupt Status Register */
#define MII_ISR 0x13
#define ISR_LINK_UP 0x0400
#define ISR_LINK_DOWN 0x0800
/* Cable-Detect-Test Control Register */
#define MII_CDTC 0x16
#define CDTC_EN_OFF 0 /* sc */
#define CDTC_EN_BITS 1
#define CDTC_PAIR_OFF 8
#define CDTC_PAIR_BIT 2
/* Cable-Detect-Test Status Register */
#define MII_CDTS 0x1C
#define CDTS_STATUS_OFF 8
#define CDTS_STATUS_BITS 2
#define CDTS_STATUS_NORMAL 0
#define CDTS_STATUS_SHORT 1
#define CDTS_STATUS_OPEN 2
#define CDTS_STATUS_INVALID 3
#define MII_DBG_ADDR 0x1D
#define MII_DBG_DATA 0x1E
#define MII_ANA_CTRL_0 0x0
#define ANA_RESTART_CAL 0x0001
#define ANA_MANUL_SWICH_ON_SHIFT 0x1
#define ANA_MANUL_SWICH_ON_MASK 0xF
#define ANA_MAN_ENABLE 0x0020
#define ANA_SEL_HSP 0x0040
#define ANA_EN_HB 0x0080
#define ANA_EN_HBIAS 0x0100
#define ANA_OEN_125M 0x0200
#define ANA_EN_LCKDT 0x0400
#define ANA_LCKDT_PHY 0x0800
#define ANA_AFE_MODE 0x1000
#define ANA_VCO_SLOW 0x2000
#define ANA_VCO_FAST 0x4000
#define ANA_SEL_CLK125M_DSP 0x8000
#define MII_ANA_CTRL_4 0x4
#define ANA_IECHO_ADJ_MASK 0xF
#define ANA_IECHO_ADJ_3_SHIFT 0
#define ANA_IECHO_ADJ_2_SHIFT 4
#define ANA_IECHO_ADJ_1_SHIFT 8
#define ANA_IECHO_ADJ_0_SHIFT 12
#define MII_ANA_CTRL_5 0x5
#define ANA_SERDES_CDR_BW_SHIFT 0
#define ANA_SERDES_CDR_BW_MASK 0x3
#define ANA_MS_PAD_DBG 0x0004
#define ANA_SPEEDUP_DBG 0x0008
#define ANA_SERDES_TH_LOS_SHIFT 4
#define ANA_SERDES_TH_LOS_MASK 0x3
#define ANA_SERDES_EN_DEEM 0x0040
#define ANA_SERDES_TXELECIDLE 0x0080
#define ANA_SERDES_BEACON 0x0100
#define ANA_SERDES_HALFTXDR 0x0200
#define ANA_SERDES_SEL_HSP 0x0400
#define ANA_SERDES_EN_PLL 0x0800
#define ANA_SERDES_EN 0x1000
#define ANA_SERDES_EN_LCKDT 0x2000
#define MII_ANA_CTRL_11 0xB
#define ANA_PS_HIB_EN 0x8000
#define MII_ANA_CTRL_18 0x12
#define ANA_TEST_MODE_10BT_01SHIFT 0
#define ANA_TEST_MODE_10BT_01MASK 0x3
#define ANA_LOOP_SEL_10BT 0x0004
#define ANA_RGMII_MODE_SW 0x0008
#define ANA_EN_LONGECABLE 0x0010
#define ANA_TEST_MODE_10BT_2 0x0020
#define ANA_EN_10BT_IDLE 0x0400
#define ANA_EN_MASK_TB 0x0800
#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
#define ANA_TRIGGER_SEL_TIMER_MASK 0x3
#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
#define ANA_INTERVAL_SEL_TIMER_MASK 0x3
#define MII_ANA_CTRL_41 0x29
#define ANA_TOP_PS_EN 0x8000
#define MII_ANA_CTRL_54 0x36
#define ANA_LONG_CABLE_TH_100_SHIFT 0
#define ANA_LONG_CABLE_TH_100_MASK 0x3F
#define ANA_DESERVED 0x0040
#define ANA_EN_LIT_CH 0x0080
#define ANA_SHORT_CABLE_TH_100_SHIFT 8
#define ANA_SHORT_CABLE_TH_100_MASK 0x3F
#define ANA_BP_BAD_LINK_ACCUM 0x4000
#define ANA_BP_SMALL_BW 0x8000
#endif /*_ATL1C_HW_H_*/

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drivers/net/atl1c/atl1c_main.c Normal file
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