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Merge branch 'topic/tegra' into for-linus
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commit
42cb6e07c5
@ -38,6 +38,9 @@
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#include "dmaengine.h"
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#define CREATE_TRACE_POINTS
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#include <trace/events/tegra_apb_dma.h>
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#define TEGRA_APBDMA_GENERAL 0x0
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#define TEGRA_APBDMA_GENERAL_ENABLE BIT(31)
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@ -146,7 +149,7 @@ struct tegra_dma_channel_regs {
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};
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/*
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* tegra_dma_sg_req: Dma request details to configure hardware. This
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* tegra_dma_sg_req: DMA request details to configure hardware. This
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* contains the details for one transfer to configure DMA hw.
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* The client's request for data transfer can be broken into multiple
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* sub-transfer as per requester details and hw support.
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@ -155,7 +158,7 @@ struct tegra_dma_channel_regs {
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*/
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struct tegra_dma_sg_req {
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struct tegra_dma_channel_regs ch_regs;
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int req_len;
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unsigned int req_len;
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bool configured;
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bool last_sg;
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struct list_head node;
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@ -169,8 +172,8 @@ struct tegra_dma_sg_req {
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*/
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struct tegra_dma_desc {
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struct dma_async_tx_descriptor txd;
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int bytes_requested;
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int bytes_transferred;
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unsigned int bytes_requested;
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unsigned int bytes_transferred;
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enum dma_status dma_status;
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struct list_head node;
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struct list_head tx_list;
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@ -186,7 +189,7 @@ typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
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/* tegra_dma_channel: Channel specific information */
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struct tegra_dma_channel {
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struct dma_chan dma_chan;
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char name[30];
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char name[12];
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bool config_init;
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int id;
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int irq;
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@ -574,7 +577,7 @@ static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
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struct tegra_dma_sg_req *hsgreq = NULL;
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if (list_empty(&tdc->pending_sg_req)) {
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dev_err(tdc2dev(tdc), "Dma is running without req\n");
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dev_err(tdc2dev(tdc), "DMA is running without req\n");
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tegra_dma_stop(tdc);
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return false;
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}
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@ -587,7 +590,7 @@ static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
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hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
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if (!hsgreq->configured) {
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tegra_dma_stop(tdc);
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dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
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dev_err(tdc2dev(tdc), "Error in DMA transfer, aborting DMA\n");
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tegra_dma_abort_all(tdc);
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return false;
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}
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@ -636,7 +639,10 @@ static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
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sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
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dma_desc = sgreq->dma_desc;
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dma_desc->bytes_transferred += sgreq->req_len;
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/* if we dma for long enough the transfer count will wrap */
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dma_desc->bytes_transferred =
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(dma_desc->bytes_transferred + sgreq->req_len) %
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dma_desc->bytes_requested;
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/* Callback need to be call */
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if (!dma_desc->cb_count)
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@ -669,6 +675,8 @@ static void tegra_dma_tasklet(unsigned long data)
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dmaengine_desc_get_callback(&dma_desc->txd, &cb);
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cb_count = dma_desc->cb_count;
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dma_desc->cb_count = 0;
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trace_tegra_dma_complete_cb(&tdc->dma_chan, cb_count,
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cb.callback);
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spin_unlock_irqrestore(&tdc->lock, flags);
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while (cb_count--)
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dmaengine_desc_callback_invoke(&cb, NULL);
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@ -685,6 +693,7 @@ static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
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spin_lock_irqsave(&tdc->lock, flags);
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trace_tegra_dma_isr(&tdc->dma_chan, irq);
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status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
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if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
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tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
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@ -843,6 +852,7 @@ found:
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dma_set_residue(txstate, residual);
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}
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trace_tegra_dma_tx_status(&tdc->dma_chan, cookie, txstate);
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spin_unlock_irqrestore(&tdc->lock, flags);
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return ret;
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}
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@ -919,7 +929,7 @@ static int get_transfer_param(struct tegra_dma_channel *tdc,
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return 0;
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default:
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dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
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dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
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return -EINVAL;
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}
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return -EINVAL;
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@ -952,7 +962,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
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enum dma_slave_buswidth slave_bw;
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if (!tdc->config_init) {
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dev_err(tdc2dev(tdc), "dma channel is not configured\n");
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dev_err(tdc2dev(tdc), "DMA channel is not configured\n");
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return NULL;
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}
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if (sg_len < 1) {
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@ -985,7 +995,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
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dma_desc = tegra_dma_desc_get(tdc);
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if (!dma_desc) {
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dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
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dev_err(tdc2dev(tdc), "DMA descriptors not available\n");
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return NULL;
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}
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INIT_LIST_HEAD(&dma_desc->tx_list);
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@ -1005,14 +1015,14 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
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if ((len & 3) || (mem & 3) ||
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(len > tdc->tdma->chip_data->max_dma_count)) {
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dev_err(tdc2dev(tdc),
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"Dma length/memory address is not supported\n");
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"DMA length/memory address is not supported\n");
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tegra_dma_desc_put(tdc, dma_desc);
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return NULL;
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}
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sg_req = tegra_dma_sg_req_get(tdc);
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if (!sg_req) {
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dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
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dev_err(tdc2dev(tdc), "DMA sg-req not available\n");
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tegra_dma_desc_put(tdc, dma_desc);
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return NULL;
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}
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@ -1087,7 +1097,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
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* terminating the DMA.
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*/
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if (tdc->busy) {
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dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
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dev_err(tdc2dev(tdc), "Request not allowed when DMA running\n");
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return NULL;
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}
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@ -1144,7 +1154,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
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while (remain_len) {
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sg_req = tegra_dma_sg_req_get(tdc);
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if (!sg_req) {
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dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
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dev_err(tdc2dev(tdc), "DMA sg-req not available\n");
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tegra_dma_desc_put(tdc, dma_desc);
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return NULL;
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}
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@ -1319,8 +1329,9 @@ static int tegra_dma_probe(struct platform_device *pdev)
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return -ENODEV;
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}
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tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
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sizeof(struct tegra_dma_channel), GFP_KERNEL);
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tdma = devm_kzalloc(&pdev->dev,
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struct_size(tdma, channels, cdata->nr_channels),
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GFP_KERNEL);
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if (!tdma)
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return -ENOMEM;
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@ -678,8 +678,9 @@ static int tegra_adma_probe(struct platform_device *pdev)
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return -ENODEV;
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}
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tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
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sizeof(struct tegra_adma_chan), GFP_KERNEL);
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tdma = devm_kzalloc(&pdev->dev,
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struct_size(tdma, channels, cdata->nr_channels),
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GFP_KERNEL);
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if (!tdma)
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return -ENOMEM;
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61
include/trace/events/tegra_apb_dma.h
Normal file
61
include/trace/events/tegra_apb_dma.h
Normal file
@ -0,0 +1,61 @@
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#if !defined(_TRACE_TEGRA_APB_DMA_H) || defined(TRACE_HEADER_MULTI_READ)
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#define _TRACE_TEGRA_APM_DMA_H
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#include <linux/tracepoint.h>
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#include <linux/dmaengine.h>
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#undef TRACE_SYSTEM
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#define TRACE_SYSTEM tegra_apb_dma
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TRACE_EVENT(tegra_dma_tx_status,
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TP_PROTO(struct dma_chan *dc, dma_cookie_t cookie, struct dma_tx_state *state),
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TP_ARGS(dc, cookie, state),
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TP_STRUCT__entry(
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__string(chan, dev_name(&dc->dev->device))
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__field(dma_cookie_t, cookie)
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__field(__u32, residue)
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),
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TP_fast_assign(
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__assign_str(chan, dev_name(&dc->dev->device));
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__entry->cookie = cookie;
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__entry->residue = state ? state->residue : (u32)-1;
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),
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TP_printk("channel %s: dma cookie %d, residue %u",
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__get_str(chan), __entry->cookie, __entry->residue)
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);
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TRACE_EVENT(tegra_dma_complete_cb,
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TP_PROTO(struct dma_chan *dc, int count, void *ptr),
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TP_ARGS(dc, count, ptr),
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TP_STRUCT__entry(
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__string(chan, dev_name(&dc->dev->device))
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__field(int, count)
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__field(void *, ptr)
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),
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TP_fast_assign(
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__assign_str(chan, dev_name(&dc->dev->device));
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__entry->count = count;
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__entry->ptr = ptr;
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),
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TP_printk("channel %s: done %d, ptr %p",
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__get_str(chan), __entry->count, __entry->ptr)
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);
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TRACE_EVENT(tegra_dma_isr,
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TP_PROTO(struct dma_chan *dc, int irq),
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TP_ARGS(dc, irq),
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TP_STRUCT__entry(
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__string(chan, dev_name(&dc->dev->device))
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__field(int, irq)
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),
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TP_fast_assign(
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__assign_str(chan, dev_name(&dc->dev->device));
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__entry->irq = irq;
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),
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TP_printk("%s: irq %d\n", __get_str(chan), __entry->irq)
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);
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#endif /* _TRACE_TEGRADMA_H */
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/* This part must be outside protection */
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#include <trace/define_trace.h>
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