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KVM: arm64: vgic-its: Implement basic ITS register handlers
Add emulation for some basic MMIO registers used in the ITS emulation.
This includes:
- GITS_{CTLR,TYPER,IIDR}
- ID registers
- GITS_{CBASER,CREADR,CWRITER}
(which implement the ITS command buffer handling)
- GITS_BASER<n>
Most of the handlers are pretty straight forward, only the CWRITER
handler is a bit more involved by taking the new its_cmd mutex and
then iterating over the command buffer.
The registers holding base addresses and attributes are sanitised before
storing them.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Andre Przywara
Marc Zyngier
parent
1085fdc68c
commit
424c33830f
@ -22,6 +22,7 @@
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <kvm/iodev.h>
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#include <linux/list.h>
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#define VGIC_V3_MAX_CPUS 255
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#define VGIC_V2_MAX_CPUS 8
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@ -136,6 +137,21 @@ struct vgic_its {
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bool enabled;
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bool initialized;
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struct vgic_io_device iodev;
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/* These registers correspond to GITS_BASER{0,1} */
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u64 baser_device_table;
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u64 baser_coll_table;
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/* Protects the command queue */
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struct mutex cmd_lock;
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u64 cbaser;
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u32 creadr;
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u32 cwriter;
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/* Protects the device and collection lists */
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struct mutex its_lock;
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struct list_head device_list;
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struct list_head collection_list;
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};
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struct vgic_dist {
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@ -21,6 +21,7 @@
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/uaccess.h>
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#include <linux/irqchip/arm-gic-v3.h>
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@ -32,6 +33,329 @@
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#include "vgic.h"
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#include "vgic-mmio.h"
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struct its_device {
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struct list_head dev_list;
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/* the head for the list of ITTEs */
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struct list_head itt_head;
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u32 device_id;
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};
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#define COLLECTION_NOT_MAPPED ((u32)~0)
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struct its_collection {
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struct list_head coll_list;
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u32 collection_id;
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u32 target_addr;
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};
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#define its_is_collection_mapped(coll) ((coll) && \
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((coll)->target_addr != COLLECTION_NOT_MAPPED))
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struct its_itte {
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struct list_head itte_list;
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struct its_collection *collection;
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u32 lpi;
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u32 event_id;
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};
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/*
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* We only implement 48 bits of PA at the moment, although the ITS
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* supports more. Let's be restrictive here.
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*/
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#define CBASER_ADDRESS(x) ((x) & GENMASK_ULL(47, 12))
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static unsigned long vgic_mmio_read_its_ctlr(struct kvm *vcpu,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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u32 reg = 0;
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mutex_lock(&its->cmd_lock);
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if (its->creadr == its->cwriter)
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reg |= GITS_CTLR_QUIESCENT;
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if (its->enabled)
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reg |= GITS_CTLR_ENABLE;
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mutex_unlock(&its->cmd_lock);
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return reg;
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}
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static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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its->enabled = !!(val & GITS_CTLR_ENABLE);
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}
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static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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u64 reg = GITS_TYPER_PLPIS;
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/*
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* We use linear CPU numbers for redistributor addressing,
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* so GITS_TYPER.PTA is 0.
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* Also we force all PROPBASER registers to be the same, so
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* CommonLPIAff is 0 as well.
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* To avoid memory waste in the guest, we keep the number of IDBits and
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* DevBits low - as least for the time being.
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*/
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reg |= 0x0f << GITS_TYPER_DEVBITS_SHIFT;
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reg |= 0x0f << GITS_TYPER_IDBITS_SHIFT;
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return extract_bytes(reg, addr & 7, len);
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}
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static unsigned long vgic_mmio_read_its_iidr(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
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}
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static unsigned long vgic_mmio_read_its_idregs(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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switch (addr & 0xffff) {
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case GITS_PIDR0:
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return 0x92; /* part number, bits[7:0] */
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case GITS_PIDR1:
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return 0xb4; /* part number, bits[11:8] */
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case GITS_PIDR2:
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return GIC_PIDR2_ARCH_GICv3 | 0x0b;
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case GITS_PIDR4:
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return 0x40; /* This is a 64K software visible page */
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/* The following are the ID registers for (any) GIC. */
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case GITS_CIDR0:
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return 0x0d;
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case GITS_CIDR1:
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return 0xf0;
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case GITS_CIDR2:
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return 0x05;
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case GITS_CIDR3:
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return 0xb1;
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}
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return 0;
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}
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/* Requires the its_lock to be held. */
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static void its_free_itte(struct kvm *kvm, struct its_itte *itte)
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{
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list_del(&itte->itte_list);
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kfree(itte);
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}
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static int vgic_its_handle_command(struct kvm *kvm, struct vgic_its *its,
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u64 *its_cmd)
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{
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return -ENODEV;
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}
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static u64 vgic_sanitise_its_baser(u64 reg)
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{
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reg = vgic_sanitise_field(reg, GITS_BASER_SHAREABILITY_MASK,
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GITS_BASER_SHAREABILITY_SHIFT,
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vgic_sanitise_shareability);
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reg = vgic_sanitise_field(reg, GITS_BASER_INNER_CACHEABILITY_MASK,
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GITS_BASER_INNER_CACHEABILITY_SHIFT,
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vgic_sanitise_inner_cacheability);
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reg = vgic_sanitise_field(reg, GITS_BASER_OUTER_CACHEABILITY_MASK,
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GITS_BASER_OUTER_CACHEABILITY_SHIFT,
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vgic_sanitise_outer_cacheability);
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/* Bits 15:12 contain bits 51:48 of the PA, which we don't support. */
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reg &= ~GENMASK_ULL(15, 12);
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/* We support only one (ITS) page size: 64K */
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reg = (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K;
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return reg;
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}
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static u64 vgic_sanitise_its_cbaser(u64 reg)
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{
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reg = vgic_sanitise_field(reg, GITS_CBASER_SHAREABILITY_MASK,
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GITS_CBASER_SHAREABILITY_SHIFT,
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vgic_sanitise_shareability);
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reg = vgic_sanitise_field(reg, GITS_CBASER_INNER_CACHEABILITY_MASK,
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GITS_CBASER_INNER_CACHEABILITY_SHIFT,
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vgic_sanitise_inner_cacheability);
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reg = vgic_sanitise_field(reg, GITS_CBASER_OUTER_CACHEABILITY_MASK,
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GITS_CBASER_OUTER_CACHEABILITY_SHIFT,
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vgic_sanitise_outer_cacheability);
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/*
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* Sanitise the physical address to be 64k aligned.
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* Also limit the physical addresses to 48 bits.
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*/
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reg &= ~(GENMASK_ULL(51, 48) | GENMASK_ULL(15, 12));
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return reg;
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}
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static unsigned long vgic_mmio_read_its_cbaser(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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return extract_bytes(its->cbaser, addr & 7, len);
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}
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static void vgic_mmio_write_its_cbaser(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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/* When GITS_CTLR.Enable is 1, this register is RO. */
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if (its->enabled)
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return;
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mutex_lock(&its->cmd_lock);
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its->cbaser = update_64bit_reg(its->cbaser, addr & 7, len, val);
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its->cbaser = vgic_sanitise_its_cbaser(its->cbaser);
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its->creadr = 0;
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/*
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* CWRITER is architecturally UNKNOWN on reset, but we need to reset
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* it to CREADR to make sure we start with an empty command buffer.
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*/
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its->cwriter = its->creadr;
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mutex_unlock(&its->cmd_lock);
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}
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#define ITS_CMD_BUFFER_SIZE(baser) ((((baser) & 0xff) + 1) << 12)
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#define ITS_CMD_SIZE 32
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#define ITS_CMD_OFFSET(reg) ((reg) & GENMASK(19, 5))
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/*
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* By writing to CWRITER the guest announces new commands to be processed.
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* To avoid any races in the first place, we take the its_cmd lock, which
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* protects our ring buffer variables, so that there is only one user
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* per ITS handling commands at a given time.
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*/
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static void vgic_mmio_write_its_cwriter(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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gpa_t cbaser;
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u64 cmd_buf[4];
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u32 reg;
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if (!its)
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return;
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mutex_lock(&its->cmd_lock);
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reg = update_64bit_reg(its->cwriter, addr & 7, len, val);
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reg = ITS_CMD_OFFSET(reg);
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if (reg >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
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mutex_unlock(&its->cmd_lock);
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return;
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}
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its->cwriter = reg;
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cbaser = CBASER_ADDRESS(its->cbaser);
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while (its->cwriter != its->creadr) {
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int ret = kvm_read_guest(kvm, cbaser + its->creadr,
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cmd_buf, ITS_CMD_SIZE);
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/*
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* If kvm_read_guest() fails, this could be due to the guest
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* programming a bogus value in CBASER or something else going
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* wrong from which we cannot easily recover.
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* According to section 6.3.2 in the GICv3 spec we can just
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* ignore that command then.
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*/
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if (!ret)
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vgic_its_handle_command(kvm, its, cmd_buf);
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its->creadr += ITS_CMD_SIZE;
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if (its->creadr == ITS_CMD_BUFFER_SIZE(its->cbaser))
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its->creadr = 0;
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}
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mutex_unlock(&its->cmd_lock);
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}
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static unsigned long vgic_mmio_read_its_cwriter(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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return extract_bytes(its->cwriter, addr & 0x7, len);
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}
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static unsigned long vgic_mmio_read_its_creadr(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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return extract_bytes(its->creadr, addr & 0x7, len);
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}
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#define BASER_INDEX(addr) (((addr) / sizeof(u64)) & 0x7)
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static unsigned long vgic_mmio_read_its_baser(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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u64 reg;
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switch (BASER_INDEX(addr)) {
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case 0:
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reg = its->baser_device_table;
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break;
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case 1:
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reg = its->baser_coll_table;
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break;
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default:
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reg = 0;
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break;
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}
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return extract_bytes(reg, addr & 7, len);
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}
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#define GITS_BASER_RO_MASK (GENMASK_ULL(52, 48) | GENMASK_ULL(58, 56))
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static void vgic_mmio_write_its_baser(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u64 entry_size, device_type;
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u64 reg, *regptr, clearbits = 0;
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/* When GITS_CTLR.Enable is 1, we ignore write accesses. */
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if (its->enabled)
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return;
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switch (BASER_INDEX(addr)) {
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case 0:
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regptr = &its->baser_device_table;
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entry_size = 8;
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device_type = GITS_BASER_TYPE_DEVICE;
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break;
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case 1:
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regptr = &its->baser_coll_table;
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entry_size = 8;
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device_type = GITS_BASER_TYPE_COLLECTION;
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clearbits = GITS_BASER_INDIRECT;
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break;
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default:
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return;
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}
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reg = update_64bit_reg(*regptr, addr & 7, len, val);
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reg &= ~GITS_BASER_RO_MASK;
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reg &= ~clearbits;
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reg |= (entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT;
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reg |= device_type << GITS_BASER_TYPE_SHIFT;
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reg = vgic_sanitise_its_baser(reg);
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*regptr = reg;
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}
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#define REGISTER_ITS_DESC(off, rd, wr, length, acc) \
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{ \
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.reg_offset = off, \
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@ -41,12 +365,6 @@
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.its_write = wr, \
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}
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static unsigned long its_mmio_read_raz(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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return 0;
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}
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static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len, unsigned long val)
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{
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@ -55,28 +373,28 @@ static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
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static struct vgic_register_region its_registers[] = {
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REGISTER_ITS_DESC(GITS_CTLR,
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its_mmio_read_raz, its_mmio_write_wi, 4,
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vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, 4,
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VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_IIDR,
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its_mmio_read_raz, its_mmio_write_wi, 4,
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vgic_mmio_read_its_iidr, its_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_TYPER,
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its_mmio_read_raz, its_mmio_write_wi, 8,
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vgic_mmio_read_its_typer, its_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_CBASER,
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its_mmio_read_raz, its_mmio_write_wi, 8,
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vgic_mmio_read_its_cbaser, vgic_mmio_write_its_cbaser, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_CWRITER,
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its_mmio_read_raz, its_mmio_write_wi, 8,
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vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_CREADR,
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its_mmio_read_raz, its_mmio_write_wi, 8,
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vgic_mmio_read_its_creadr, its_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_BASER,
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its_mmio_read_raz, its_mmio_write_wi, 0x40,
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vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, 0x40,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_IDREGS_BASE,
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its_mmio_read_raz, its_mmio_write_wi, 0x30,
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vgic_mmio_read_its_idregs, its_mmio_write_wi, 0x30,
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VGIC_ACCESS_32bit),
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};
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@ -109,6 +427,18 @@ static int vgic_its_init_its(struct kvm *kvm, struct vgic_its *its)
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return ret;
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}
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#define INITIAL_BASER_VALUE \
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(GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) | \
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GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, SameAsInner) | \
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GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) | \
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((8ULL - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | \
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GITS_BASER_PAGE_SIZE_64K)
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#define INITIAL_PROPBASER_VALUE \
|
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(GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb) | \
|
||||
GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, SameAsInner) | \
|
||||
GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable))
|
||||
|
||||
static int vgic_its_create(struct kvm_device *dev, u32 type)
|
||||
{
|
||||
struct vgic_its *its;
|
||||
@ -120,12 +450,24 @@ static int vgic_its_create(struct kvm_device *dev, u32 type)
|
||||
if (!its)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&its->its_lock);
|
||||
mutex_init(&its->cmd_lock);
|
||||
|
||||
its->vgic_its_base = VGIC_ADDR_UNDEF;
|
||||
|
||||
INIT_LIST_HEAD(&its->device_list);
|
||||
INIT_LIST_HEAD(&its->collection_list);
|
||||
|
||||
dev->kvm->arch.vgic.has_its = true;
|
||||
its->initialized = false;
|
||||
its->enabled = false;
|
||||
|
||||
its->baser_device_table = INITIAL_BASER_VALUE |
|
||||
((u64)GITS_BASER_TYPE_DEVICE << GITS_BASER_TYPE_SHIFT);
|
||||
its->baser_coll_table = INITIAL_BASER_VALUE |
|
||||
((u64)GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT);
|
||||
dev->kvm->arch.vgic.propbaser = INITIAL_PROPBASER_VALUE;
|
||||
|
||||
dev->private = its;
|
||||
|
||||
return 0;
|
||||
@ -133,7 +475,36 @@ static int vgic_its_create(struct kvm_device *dev, u32 type)
|
||||
|
||||
static void vgic_its_destroy(struct kvm_device *kvm_dev)
|
||||
{
|
||||
struct kvm *kvm = kvm_dev->kvm;
|
||||
struct vgic_its *its = kvm_dev->private;
|
||||
struct its_device *dev;
|
||||
struct its_itte *itte;
|
||||
struct list_head *dev_cur, *dev_temp;
|
||||
struct list_head *cur, *temp;
|
||||
|
||||
/*
|
||||
* We may end up here without the lists ever having been initialized.
|
||||
* Check this and bail out early to avoid dereferencing a NULL pointer.
|
||||
*/
|
||||
if (!its->device_list.next)
|
||||
return;
|
||||
|
||||
mutex_lock(&its->its_lock);
|
||||
list_for_each_safe(dev_cur, dev_temp, &its->device_list) {
|
||||
dev = container_of(dev_cur, struct its_device, dev_list);
|
||||
list_for_each_safe(cur, temp, &dev->itt_head) {
|
||||
itte = (container_of(cur, struct its_itte, itte_list));
|
||||
its_free_itte(kvm, itte);
|
||||
}
|
||||
list_del(dev_cur);
|
||||
kfree(dev);
|
||||
}
|
||||
|
||||
list_for_each_safe(cur, temp, &its->collection_list) {
|
||||
list_del(cur);
|
||||
kfree(container_of(cur, struct its_collection, coll_list));
|
||||
}
|
||||
mutex_unlock(&its->its_lock);
|
||||
|
||||
kfree(its);
|
||||
}
|
||||
|
||||
@ -23,15 +23,15 @@
|
||||
#include "vgic-mmio.h"
|
||||
|
||||
/* extract @num bytes at @offset bytes offset in data */
|
||||
static unsigned long extract_bytes(unsigned long data, unsigned int offset,
|
||||
unsigned int num)
|
||||
unsigned long extract_bytes(unsigned long data, unsigned int offset,
|
||||
unsigned int num)
|
||||
{
|
||||
return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
|
||||
}
|
||||
|
||||
/* allows updates of any half of a 64-bit register (or the whole thing) */
|
||||
static u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
|
||||
unsigned long val)
|
||||
u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
|
||||
unsigned long val)
|
||||
{
|
||||
int lower = (offset & 4) * 8;
|
||||
int upper = lower + 8 * len - 1;
|
||||
|
||||
@ -96,6 +96,12 @@ unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len);
|
||||
void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
|
||||
unsigned long data);
|
||||
|
||||
unsigned long extract_bytes(unsigned long data, unsigned int offset,
|
||||
unsigned int num);
|
||||
|
||||
u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
|
||||
unsigned long val);
|
||||
|
||||
unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
|
||||
gpa_t addr, unsigned int len);
|
||||
|
||||
|
||||
@ -33,10 +33,16 @@ struct vgic_global __section(.hyp.text) kvm_vgic_global_state;
|
||||
|
||||
/*
|
||||
* Locking order is always:
|
||||
* vgic_cpu->ap_list_lock
|
||||
* vgic_irq->irq_lock
|
||||
* its->cmd_lock (mutex)
|
||||
* its->its_lock (mutex)
|
||||
* vgic_cpu->ap_list_lock
|
||||
* vgic_irq->irq_lock
|
||||
*
|
||||
* (that is, always take the ap_list_lock before the struct vgic_irq lock).
|
||||
* If you need to take multiple locks, always take the upper lock first,
|
||||
* then the lower ones, e.g. first take the its_lock, then the irq_lock.
|
||||
* If you are already holding a lock and need to take a higher one, you
|
||||
* have to drop the lower ranking lock first and re-aquire it after having
|
||||
* taken the upper one.
|
||||
*
|
||||
* When taking more than one ap_list_lock at the same time, always take the
|
||||
* lowest numbered VCPU's ap_list_lock first, so:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user