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bnxt_en: Modify the ring reservation functions for 57500 series chips.
The ring reservation functions have to be modified for P5 chips in the following ways: - bnxt_cp_ring_info structs map to internal NQs as well as CP rings. - Ring groups are not used. - 1 CP ring must be available for each RX or TX ring. - number of RSS contexts to reserve is multiples of 64 RX rings. - RFS currently not supported. Also, RX AGG rings are only used for jumbo frames, so we need to unconditionally call bnxt_reserve_rings() in __bnxt_open_nic() to see if we need to reserve AGG rings in case MTU has changed. Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
9c1fabdf42
commit
41e8d79837
@ -4330,7 +4330,8 @@ static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
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if (!rc) {
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u32 flags = le32_to_cpu(resp->flags);
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if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)
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if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
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(flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
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bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
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if (flags &
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VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
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@ -4713,6 +4714,9 @@ static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
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}
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}
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static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
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bool shared);
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static int bnxt_hwrm_get_rings(struct bnxt *bp)
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{
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struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
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@ -4743,6 +4747,22 @@ static int bnxt_hwrm_get_rings(struct bnxt *bp)
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cp = le16_to_cpu(resp->alloc_cmpl_rings);
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stats = le16_to_cpu(resp->alloc_stat_ctx);
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cp = min_t(u16, cp, stats);
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if (bp->flags & BNXT_FLAG_CHIP_P5) {
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int rx = hw_resc->resv_rx_rings;
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int tx = hw_resc->resv_tx_rings;
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if (bp->flags & BNXT_FLAG_AGG_RINGS)
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rx >>= 1;
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if (cp < (rx + tx)) {
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bnxt_trim_rings(bp, &rx, &tx, cp, false);
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if (bp->flags & BNXT_FLAG_AGG_RINGS)
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rx <<= 1;
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hw_resc->resv_rx_rings = rx;
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hw_resc->resv_tx_rings = tx;
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}
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cp = le16_to_cpu(resp->alloc_msix);
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hw_resc->resv_hw_ring_grps = rx;
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}
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hw_resc->resv_cp_rings = cp;
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}
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mutex_unlock(&bp->hwrm_cmd_lock);
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@ -4768,6 +4788,8 @@ int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
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return rc;
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}
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static bool bnxt_rfs_supported(struct bnxt *bp);
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static void
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__bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
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int tx_rings, int rx_rings, int ring_grps,
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@ -4781,15 +4803,38 @@ __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
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req->num_tx_rings = cpu_to_le16(tx_rings);
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if (BNXT_NEW_RM(bp)) {
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enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
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enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
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FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
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enables |= ring_grps ?
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FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
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if (bp->flags & BNXT_FLAG_CHIP_P5) {
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enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
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enables |= tx_rings + ring_grps ?
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FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
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FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
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enables |= rx_rings ?
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FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
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} else {
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enables |= cp_rings ?
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FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
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FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
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enables |= ring_grps ?
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FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
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FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
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}
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enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
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req->num_rx_rings = cpu_to_le16(rx_rings);
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req->num_hw_ring_grps = cpu_to_le16(ring_grps);
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req->num_cmpl_rings = cpu_to_le16(cp_rings);
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if (bp->flags & BNXT_FLAG_CHIP_P5) {
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req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
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req->num_msix = cpu_to_le16(cp_rings);
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req->num_rsscos_ctxs =
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cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
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} else {
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req->num_cmpl_rings = cpu_to_le16(cp_rings);
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req->num_hw_ring_grps = cpu_to_le16(ring_grps);
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req->num_rsscos_ctxs = cpu_to_le16(1);
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if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
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bnxt_rfs_supported(bp))
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req->num_rsscos_ctxs =
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cpu_to_le16(ring_grps + 1);
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}
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req->num_stat_ctxs = req->num_cmpl_rings;
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req->num_vnics = cpu_to_le16(vnics);
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}
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@ -4806,16 +4851,33 @@ __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
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bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
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enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
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enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
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enables |= cp_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
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FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
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enables |= ring_grps ? FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
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enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
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FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
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if (bp->flags & BNXT_FLAG_CHIP_P5) {
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enables |= tx_rings + ring_grps ?
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FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
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FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
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} else {
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enables |= cp_rings ?
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FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
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FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
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enables |= ring_grps ?
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FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
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}
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enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
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enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
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req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
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req->num_tx_rings = cpu_to_le16(tx_rings);
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req->num_rx_rings = cpu_to_le16(rx_rings);
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req->num_hw_ring_grps = cpu_to_le16(ring_grps);
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req->num_cmpl_rings = cpu_to_le16(cp_rings);
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if (bp->flags & BNXT_FLAG_CHIP_P5) {
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req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
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req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
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} else {
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req->num_cmpl_rings = cpu_to_le16(cp_rings);
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req->num_hw_ring_grps = cpu_to_le16(ring_grps);
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req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
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}
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req->num_stat_ctxs = req->num_cmpl_rings;
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req->num_vnics = cpu_to_le16(vnics);
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@ -4859,10 +4921,6 @@ bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
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__bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
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cp_rings, vnics);
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req.enables |= cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS |
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FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS);
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req.num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
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req.num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
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rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
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if (rc)
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return -ENOMEM;
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@ -4908,20 +4966,19 @@ static bool bnxt_need_reserve_rings(struct bnxt *bp)
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if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
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return true;
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if (bp->flags & BNXT_FLAG_RFS)
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if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
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vnic = rx + 1;
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if (bp->flags & BNXT_FLAG_AGG_RINGS)
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rx <<= 1;
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if (BNXT_NEW_RM(bp) &&
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(hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
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hw_resc->resv_hw_ring_grps != grp || hw_resc->resv_vnics != vnic))
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hw_resc->resv_vnics != vnic ||
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(hw_resc->resv_hw_ring_grps != grp &&
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!(bp->flags & BNXT_FLAG_CHIP_P5))))
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return true;
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return false;
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}
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static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
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bool shared);
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static int __bnxt_reserve_rings(struct bnxt *bp)
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{
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struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
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@ -4937,7 +4994,7 @@ static int __bnxt_reserve_rings(struct bnxt *bp)
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if (bp->flags & BNXT_FLAG_SHARED_RINGS)
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sh = true;
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if (bp->flags & BNXT_FLAG_RFS)
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if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
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vnic = rx + 1;
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if (bp->flags & BNXT_FLAG_AGG_RINGS)
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rx <<= 1;
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@ -5000,9 +5057,11 @@ static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
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flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
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FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
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FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
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FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
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FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
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FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
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FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
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FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
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if (!(bp->flags & BNXT_FLAG_CHIP_P5))
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flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
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req.flags = cpu_to_le32(flags);
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rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
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@ -5021,12 +5080,16 @@ static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
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__bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
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cp_rings, vnics);
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flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
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if (BNXT_NEW_RM(bp))
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if (BNXT_NEW_RM(bp)) {
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flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
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FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
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FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
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FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
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FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
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if (bp->flags & BNXT_FLAG_CHIP_P5)
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flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
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else
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flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
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}
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req.flags = cpu_to_le32(flags);
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rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
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@ -7505,10 +7568,10 @@ static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
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netdev_err(bp->dev, "Failed to reserve default rings at open\n");
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return rc;
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}
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rc = bnxt_reserve_rings(bp);
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if (rc)
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return rc;
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}
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rc = bnxt_reserve_rings(bp);
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if (rc)
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return rc;
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if ((bp->flags & BNXT_FLAG_RFS) &&
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!(bp->flags & BNXT_FLAG_USING_MSIX)) {
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/* disable RFS if falling back to INTA */
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@ -7980,6 +8043,8 @@ static bool bnxt_can_reserve_rings(struct bnxt *bp)
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/* If the chip and firmware supports RFS */
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static bool bnxt_rfs_supported(struct bnxt *bp)
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{
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if (bp->flags & BNXT_FLAG_CHIP_P5)
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return false;
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if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
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return true;
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if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
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@ -7993,6 +8058,8 @@ static bool bnxt_rfs_capable(struct bnxt *bp)
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#ifdef CONFIG_RFS_ACCEL
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int vnics, max_vnics, max_rss_ctxs;
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if (bp->flags & BNXT_FLAG_CHIP_P5)
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return false;
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if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
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return false;
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