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irqchip: Prepare for local stub header removal

Browse Source 
The IRQCHIP_DECLARE macro moved to to 'include/linux/irqchip.h', so
the local irqchip.h became an empty shell, which solely includes
include/linux/irqchip.h

Include the global header in all irqchip drivers instead of the local
header, so we can remove it.

Signed-off-by: Joel Porquet <joel@porquet.org>
Cc: vgupta@synopsys.com
Cc: monstr@monstr.eu
Cc: ralf@linux-mips.org
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1882096.X39jVG8e0D@joel-zenbook
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Joel Porquet 2015-07-07 17:11:46 -04:00 committed by Thomas Gleixner
parent d452bca82d
commit 41a83e06e2
44 changed files with 42 additions and 79 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/irqchip/exynos-combiner.c
View File

@ -15,13 +15,12 @@
#include <linux/slab.h>
#include <linux/syscore_ops.h>
#include <linux/irqdomain.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/interrupt.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include "irqchip.h"
#define COMBINER_ENABLE_SET 0x0
#define COMBINER_ENABLE_CLEAR 0x4
#define COMBINER_INT_STATUS 0xC

3
drivers/irqchip/irq-armada-370-xp.c
View File

@ -18,6 +18,7 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/cpu.h>
#include <linux/io.h>
@ -33,8 +34,6 @@
#include <asm/smp_plat.h>
#include <asm/mach/irq.h>
#include "irqchip.h"
/* Interrupt Controller Registers Map */
#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)

2
drivers/irqchip/irq-atmel-aic.c
View File

@ -19,6 +19,7 @@
#include <linux/bitmap.h>
#include <linux/types.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@ -31,7 +32,6 @@
#include <asm/mach/irq.h>
#include "irq-atmel-aic-common.h"
#include "irqchip.h"
/* Number of irq lines managed by AIC */
#define NR_AIC_IRQS 32

2
drivers/irqchip/irq-atmel-aic5.c
View File

@ -19,6 +19,7 @@
#include <linux/bitmap.h>
#include <linux/types.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@ -31,7 +32,6 @@
#include <asm/mach/irq.h>
#include "irq-atmel-aic-common.h"
#include "irqchip.h"
/* Number of irq lines managed by AIC */
#define NR_AIC5_IRQS 128

3
drivers/irqchip/irq-bcm2835.c
View File

@ -48,13 +48,12 @@
#include <linux/slab.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <asm/exception.h>
#include <asm/mach/irq.h>
#include "irqchip.h"
/* Put the bank and irq (32 bits) into the hwirq */
#define MAKE_HWIRQ(b, n) ((b << 5) | (n))
#define HWIRQ_BANK(i) (i >> 5)

3
drivers/irqchip/irq-bcm7038-l1.c
View File

@ -29,10 +29,9 @@
#include <linux/slab.h>
#include <linux/smp.h>
#include <linux/types.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include "irqchip.h"
#define IRQS_PER_WORD 32
#define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
#define MAX_WORDS 8

3
drivers/irqchip/irq-bcm7120-l2.c
View File

@ -26,10 +26,9 @@
#include <linux/irqdomain.h>
#include <linux/reboot.h>
#include <linux/bitops.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include "irqchip.h"
/* Register offset in the L2 interrupt controller */
#define IRQEN 0x00
#define IRQSTAT 0x04

2
drivers/irqchip/irq-brcmstb-l2.c
View File

@ -32,8 +32,6 @@
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include "irqchip.h"
/* Register offsets in the L2 interrupt controller */
#define CPU_STATUS 0x00
#define CPU_SET 0x04

3
drivers/irqchip/irq-clps711x.c
View File

@ -11,6 +11,7 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@ -19,8 +20,6 @@
#include <asm/exception.h>
#include <asm/mach/irq.h>
#include "irqchip.h"
#define CLPS711X_INTSR1 (0x0240)
#define CLPS711X_INTMR1 (0x0280)
#define CLPS711X_BLEOI (0x0600)

3
drivers/irqchip/irq-crossbar.c
View File

@ -11,13 +11,12 @@
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include "irqchip.h"
#define IRQ_FREE -1
#define IRQ_RESERVED -2
#define IRQ_SKIP -3

3
drivers/irqchip/irq-digicolor.c
View File

@ -12,6 +12,7 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@ -20,8 +21,6 @@
#include <asm/exception.h>
#include "irqchip.h"
#define UC_IRQ_CONTROL 0x04
#define IC_FLAG_CLEAR_LO 0x00

3
drivers/irqchip/irq-dw-apb-ictl.c
View File

@ -13,12 +13,11 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include "irqchip.h"
#define APB_INT_ENABLE_L 0x00
#define APB_INT_ENABLE_H 0x04
#define APB_INT_MASK_L 0x08

3
drivers/irqchip/irq-gic-v3-its.c
View File

@ -30,14 +30,13 @@
#include <linux/percpu.h>
#include <linux/slab.h>
#include <linux/irqchip.h>
#include <linux/irqchip/arm-gic-v3.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include <asm/exception.h>
#include "irqchip.h"
#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1 << 0)
#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)

2
drivers/irqchip/irq-gic-v3.c
View File

@ -25,6 +25,7 @@
#include <linux/percpu.h>
#include <linux/slab.h>
#include <linux/irqchip.h>
#include <linux/irqchip/arm-gic-v3.h>
#include <asm/cputype.h>
@ -32,7 +33,6 @@
#include <asm/smp_plat.h>
#include "irq-gic-common.h"
#include "irqchip.h"
struct redist_region {
void __iomem *redist_base;

2
drivers/irqchip/irq-gic.c
View File

@ -38,6 +38,7 @@
#include <linux/interrupt.h>
#include <linux/percpu.h>
#include <linux/slab.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/irqchip/arm-gic-acpi.h>
@ -48,7 +49,6 @@
#include <asm/smp_plat.h>
#include "irq-gic-common.h"
#include "irqchip.h"
union gic_base {
void __iomem *common_base;

2
drivers/irqchip/irq-hip04.c
View File

@ -41,6 +41,7 @@
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/irqchip.h>
#include <linux/irqchip/arm-gic.h>
#include <asm/irq.h>
@ -48,7 +49,6 @@
#include <asm/smp_plat.h>
#include "irq-gic-common.h"
#include "irqchip.h"
#define HIP04_MAX_IRQS 510

3
drivers/irqchip/irq-ingenic.c
View File

@ -18,6 +18,7 @@
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/irqchip.h>
#include <linux/irqchip/ingenic.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@ -28,8 +29,6 @@
#include <asm/io.h>
#include <asm/mach-jz4740/irq.h>
#include "irqchip.h"
struct ingenic_intc_data {
void __iomem *base;
unsigned num_chips;

3
drivers/irqchip/irq-keystone.c
View File

@ -20,13 +20,12 @@
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/irqdomain.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include "irqchip.h"
/* The source ID bits start from 4 to 31 (total 28 bits)*/
#define BIT_OFS 4

3
drivers/irqchip/irq-mips-cpu.c
View File

@ -31,6 +31,7 @@
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <asm/irq_cpu.h>
@ -38,8 +39,6 @@
#include <asm/mipsmtregs.h>
#include <asm/setup.h>
#include "irqchip.h"
static inline void unmask_mips_irq(struct irq_data *d)
{
set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));

3
drivers/irqchip/irq-mips-gic.c
View File

@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/mips-gic.h>
#include <linux/of_address.h>
#include <linux/sched.h>
@ -22,8 +23,6 @@
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include "irqchip.h"
unsigned int gic_present;
struct gic_pcpu_mask {

3
drivers/irqchip/irq-mmp.c
View File

@ -15,6 +15,7 @@
#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/ioport.h>
@ -24,8 +25,6 @@
#include <asm/exception.h>
#include <asm/hardirq.h>
#include "irqchip.h"
#define MAX_ICU_NR 16
#define PJ1_INT_SEL 0x10c

3
drivers/irqchip/irq-moxart.c
View File

@ -12,6 +12,7 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@ -19,8 +20,6 @@
#include <asm/exception.h>
#include "irqchip.h"
#define IRQ_SOURCE_REG 0
#define IRQ_MASK_REG 0x04
#define IRQ_CLEAR_REG 0x08

3
drivers/irqchip/irq-mtk-sysirq.c
View File

@ -13,6 +13,7 @@
*/
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_irq.h>
@ -21,8 +22,6 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
#include "irqchip.h"
struct mtk_sysirq_chip_data {
spinlock_t lock;
void __iomem *intpol_base;

3
drivers/irqchip/irq-mxs.c
View File

@ -19,6 +19,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
@ -27,8 +28,6 @@
#include <linux/stmp_device.h>
#include <asm/exception.h>
#include "irqchip.h"
#define HW_ICOLL_VECTOR 0x0000
#define HW_ICOLL_LEVELACK 0x0010
#define HW_ICOLL_CTRL 0x0020

3
drivers/irqchip/irq-nvic.c
View File

@ -21,13 +21,12 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <asm/v7m.h>
#include <asm/exception.h>
#include "irqchip.h"
#define NVIC_ISER 0x000
#define NVIC_ICER 0x080
#define NVIC_IPR 0x300

3
drivers/irqchip/irq-omap-intc.c
View File

@ -17,13 +17,12 @@
#include <linux/io.h>
#include <asm/exception.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include "irqchip.h"
/* Define these here for now until we drop all board-files */
#define OMAP24XX_IC_BASE 0x480fe000
#define OMAP34XX_IC_BASE 0x48200000

3
drivers/irqchip/irq-or1k-pic.c
View File

@ -9,12 +9,11 @@
*/
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include "irqchip.h"
/* OR1K PIC implementation */
struct or1k_pic_dev {

3
drivers/irqchip/irq-orion.c
View File

@ -10,14 +10,13 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/exception.h>
#include <asm/mach/irq.h>
#include "irqchip.h"
/*
* Orion SoC main interrupt controller
*/

2
drivers/irqchip/irq-renesas-h8300h.c
View File

@ -11,8 +11,6 @@
#include <linux/of_irq.h>
#include <asm/io.h>
#include "irqchip.h"
static const char ipr_bit[] = {
7, 6, 5, 5,
4, 4, 4, 4, 3, 3, 3, 3,

2
drivers/irqchip/irq-renesas-h8s.c
View File

@ -5,10 +5,10 @@
*/
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/io.h>
#include "irqchip.h"
static void *intc_baseaddr;
#define IPRA ((unsigned long)intc_baseaddr)

3
drivers/irqchip/irq-s3c24xx.c
View File

@ -25,6 +25,7 @@
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/irqdomain.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/of.h>
#include <linux/of_irq.h>
@ -40,8 +41,6 @@
#include <plat/regs-irqtype.h>
#include <plat/pm.h>
#include "irqchip.h"
#define S3C_IRQTYPE_NONE 0
#define S3C_IRQTYPE_EINT 1
#define S3C_IRQTYPE_EDGE 2

2
drivers/irqchip/irq-sirfsoc.c
View File

@ -11,11 +11,11 @@
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/syscore_ops.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>
#include "irqchip.h"
#define SIRFSOC_INT_RISC_MASK0 0x0018
#define SIRFSOC_INT_RISC_MASK1 0x001C

3
drivers/irqchip/irq-sun4i.c
View File

@ -16,6 +16,7 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@ -23,8 +24,6 @@
#include <asm/exception.h>
#include <asm/mach/irq.h>
#include "irqchip.h"
#define SUN4I_IRQ_VECTOR_REG 0x00
#define SUN4I_IRQ_PROTECTION_REG 0x08
#define SUN4I_IRQ_NMI_CTRL_REG 0x0c

2
drivers/irqchip/irq-sunxi-nmi.c
View File

@ -17,8 +17,8 @@
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include "irqchip.h"
#define SUNXI_NMI_SRC_TYPE_MASK 0x00000003

2
drivers/irqchip/irq-tb10x.c
View File

@ -22,13 +22,13 @@
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include "irqchip.h"
#define AB_IRQCTL_INT_ENABLE 0x00
#define AB_IRQCTL_INT_STATUS 0x04

3
drivers/irqchip/irq-tegra.c
View File

@ -24,6 +24,7 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/slab.h>
@ -31,8 +32,6 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "irqchip.h"
#define ICTLR_CPU_IEP_VFIQ 0x08
#define ICTLR_CPU_IEP_FIR 0x14
#define ICTLR_CPU_IEP_FIR_SET 0x18

3
drivers/irqchip/irq-versatile-fpga.c
View File

@ -4,6 +4,7 @@
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/irqchip/versatile-fpga.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
@ -14,8 +15,6 @@
#include <asm/exception.h>
#include <asm/mach/irq.h>
#include "irqchip.h"
#define IRQ_STATUS 0x00
#define IRQ_RAW_STATUS 0x04
#define IRQ_ENABLE_SET 0x08

3
drivers/irqchip/irq-vf610-mscm-ir.c
View File

@ -26,6 +26,7 @@
#include <linux/cpu_pm.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/mfd/syscon.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -34,8 +35,6 @@
#include <linux/slab.h>
#include <linux/regmap.h>
#include "irqchip.h"
#define MSCM_CPxNUM 0x4
#define MSCM_IRSPRC(n) (0x80 + 2 * (n))

3
drivers/irqchip/irq-vic.c
View File

@ -24,6 +24,7 @@
#include <linux/list.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
@ -37,8 +38,6 @@
#include <asm/exception.h>
#include <asm/irq.h>
#include "irqchip.h"
#define VIC_IRQ_STATUS 0x00
#define VIC_FIQ_STATUS 0x04
#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */

3
drivers/irqchip/irq-vt8500.c
View File

@ -27,6 +27,7 @@
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
@ -39,8 +40,6 @@
#include <asm/exception.h>
#include <asm/mach/irq.h>
#include "irqchip.h"
#define VT8500_ICPC_IRQ 0x20
#define VT8500_ICPC_FIQ 0x24
#define VT8500_ICDC 0x40 /* Destination Control 64*u32 */

3
drivers/irqchip/irq-xtensa-mx.c
View File

@ -11,12 +11,11 @@
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <asm/mxregs.h>
#include "irqchip.h"
#define HW_IRQ_IPI_COUNT 2
#define HW_IRQ_MX_BASE 2
#define HW_IRQ_EXTERN_BASE 3

3
drivers/irqchip/irq-xtensa-pic.c
View File

@ -15,10 +15,9 @@
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include "irqchip.h"
unsigned int cached_irq_mask;
/*

3
drivers/irqchip/irq-zevio.c
View File

@ -11,6 +11,7 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@ -18,8 +19,6 @@
#include <asm/mach/irq.h>
#include <asm/exception.h>
#include "irqchip.h"
#define IO_STATUS 0x000
#define IO_RAW_STATUS 0x004
#define IO_ENABLE 0x008

3
drivers/irqchip/spear-shirq.c
View File

@ -18,14 +18,13 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/spinlock.h>
#include "irqchip.h"
/*
* struct spear_shirq: shared irq structure
*