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Cleanup decoding of MIPSxx config registers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
cd21dfcfbb
commit
4194318c39
@ -2,9 +2,9 @@
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* Processor capabilities determination functions.
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*
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* Copyright (C) xxxx the Anonymous
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* Copyright (C) 2003 Maciej W. Rozycki
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* Copyright (C) 2003, 2004 Maciej W. Rozycki
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* Copyright (C) 1994 - 2003 Ralf Baechle
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* Copyright (C) 2001 MIPS Inc.
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* Copyright (C) 2001, 2004 MIPS Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -415,69 +415,126 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
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}
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}
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static inline void decode_config1(struct cpuinfo_mips *c)
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static inline unsigned int decode_config0(struct cpuinfo_mips *c)
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{
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unsigned long config0 = read_c0_config();
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unsigned long config1;
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unsigned int config0;
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int isa;
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if ((config0 & (1 << 31)) == 0)
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return; /* actually wort a panic() */
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config0 = read_c0_config();
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if (((config0 & MIPS_CONF_MT) >> 7) == 1)
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c->options |= MIPS_CPU_TLB;
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isa = (config0 & MIPS_CONF_AT) >> 13;
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switch (isa) {
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case 0:
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c->isa_level = MIPS_CPU_ISA_M32;
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break;
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case 2:
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c->isa_level = MIPS_CPU_ISA_M64;
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break;
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default:
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panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
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}
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return config0 & MIPS_CONF_M;
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}
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static inline unsigned int decode_config1(struct cpuinfo_mips *c)
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{
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unsigned int config1;
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/* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
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c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
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MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
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MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
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config1 = read_c0_config1();
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if (config1 & (1 << 3))
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if (config1 & MIPS_CONF1_MD)
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c->ases |= MIPS_ASE_MDMX;
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if (config1 & MIPS_CONF1_WR)
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c->options |= MIPS_CPU_WATCH;
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if (config1 & (1 << 2))
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c->options |= MIPS_CPU_MIPS16;
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if (config1 & (1 << 1))
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if (config1 & MIPS_CONF1_CA)
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c->ases |= MIPS_ASE_MIPS16;
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if (config1 & MIPS_CONF1_EP)
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c->options |= MIPS_CPU_EJTAG;
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if (config1 & 1) {
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if (config1 & MIPS_CONF1_FP) {
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c->options |= MIPS_CPU_FPU;
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c->options |= MIPS_CPU_32FPR;
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}
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if (cpu_has_tlb)
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c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
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return config1 & MIPS_CONF_M;
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}
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static inline unsigned int decode_config2(struct cpuinfo_mips *c)
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{
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unsigned int config2;
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config2 = read_c0_config2();
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if (config2 & MIPS_CONF2_SL)
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c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
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return config2 & MIPS_CONF_M;
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}
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static inline unsigned int decode_config3(struct cpuinfo_mips *c)
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{
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unsigned int config3;
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config3 = read_c0_config3();
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if (config3 & MIPS_CONF3_SM)
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c->ases |= MIPS_ASE_SMARTMIPS;
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return config3 & MIPS_CONF_M;
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}
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static inline void decode_configs(struct cpuinfo_mips *c)
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{
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/* MIPS32 or MIPS64 compliant CPU. */
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c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
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MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
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c->scache.flags = MIPS_CACHE_NOT_PRESENT;
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c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
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/* Read Config registers. */
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if (!decode_config0(c))
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return; /* actually worth a panic() */
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if (!decode_config1(c))
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return;
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if (!decode_config2(c))
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return;
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if (!decode_config3(c))
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return;
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}
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static inline void cpu_probe_mips(struct cpuinfo_mips *c)
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{
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decode_config1(c);
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decode_configs(c);
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if (cpu_has_tlb)
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c->options |= MIPS_CPU_4KTLB;
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switch (c->processor_id & 0xff00) {
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case PRID_IMP_4KC:
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c->cputype = CPU_4KC;
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c->isa_level = MIPS_CPU_ISA_M32;
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break;
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case PRID_IMP_4KEC:
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c->cputype = CPU_4KEC;
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c->isa_level = MIPS_CPU_ISA_M32;
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break;
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case PRID_IMP_4KECR2:
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c->cputype = CPU_4KEC;
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c->isa_level = MIPS_CPU_ISA_M32;
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break;
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case PRID_IMP_4KSC:
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c->cputype = CPU_4KSC;
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c->isa_level = MIPS_CPU_ISA_M32;
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break;
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case PRID_IMP_5KC:
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c->cputype = CPU_5KC;
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c->isa_level = MIPS_CPU_ISA_M64;
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break;
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case PRID_IMP_20KC:
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c->cputype = CPU_20KC;
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c->isa_level = MIPS_CPU_ISA_M64;
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break;
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case PRID_IMP_24K:
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c->cputype = CPU_24K;
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c->isa_level = MIPS_CPU_ISA_M32;
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break;
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case PRID_IMP_25KF:
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c->cputype = CPU_25KF;
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c->isa_level = MIPS_CPU_ISA_M64;
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/* Probe for L2 cache */
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c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
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break;
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@ -486,7 +543,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
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static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
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{
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decode_config1(c);
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decode_configs(c);
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switch (c->processor_id & 0xff00) {
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case PRID_IMP_AU1_REV1:
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case PRID_IMP_AU1_REV2:
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@ -510,25 +567,19 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
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panic("Unknown Au Core!");
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break;
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}
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c->isa_level = MIPS_CPU_ISA_M32;
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break;
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}
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}
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static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
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{
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decode_config1(c);
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decode_configs(c);
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switch (c->processor_id & 0xff00) {
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case PRID_IMP_SB1:
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c->cputype = CPU_SB1;
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c->isa_level = MIPS_CPU_ISA_M64;
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c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
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MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
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MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
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MIPS_CPU_WATCH | MIPS_CPU_LLSC;
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#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
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#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
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/* FPU in pass1 is known to have issues. */
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c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
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c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
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#endif
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break;
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}
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@ -536,14 +587,12 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
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static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
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{
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decode_config1(c);
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decode_configs(c);
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if (cpu_has_tlb)
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c->options |= MIPS_CPU_4KTLB;
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switch (c->processor_id & 0xff00) {
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case PRID_IMP_SR71000:
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c->cputype = CPU_SR71000;
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c->isa_level = MIPS_CPU_ISA_M64;
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c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
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MIPS_CPU_4KTLB | MIPS_CPU_FPU |
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MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
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c->scache.ways = 8;
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c->tlbsize = 64;
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break;
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@ -572,15 +621,21 @@ __init void cpu_probe(void)
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case PRID_COMP_SIBYTE:
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cpu_probe_sibyte(c);
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break;
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case PRID_COMP_SANDCRAFT:
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cpu_probe_sandcraft(c);
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break;
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default:
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c->cputype = CPU_UNKNOWN;
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}
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if (c->options & MIPS_CPU_FPU)
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if (c->options & MIPS_CPU_FPU) {
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c->fpu_id = cpu_get_fpu_id();
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if (c->isa_level == MIPS_CPU_ISA_M32 ||
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c->isa_level == MIPS_CPU_ISA_M64) {
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if (c->fpu_id & MIPS_FPIR_3D)
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c->ases |= MIPS_ASE_MIPS3D;
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}
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}
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}
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__init void cpu_report(void)
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@ -2,7 +2,8 @@
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* linux/arch/mips/kernel/proc.c
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*
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* Copyright (C) 1995, 1996, 2001 Ralf Baechle
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* Copyright (C) 2001 MIPS Technologies, Inc.
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* Copyright (C) 2001, 2004 MIPS Technologies, Inc.
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* Copyright (C) 2004 Maciej W. Rozycki
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*/
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#include <linux/config.h>
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#include <linux/delay.h>
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@ -118,6 +119,11 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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cpu_has_divec ? "yes" : "no");
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seq_printf(m, "hardware watchpoint\t: %s\n",
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cpu_has_watch ? "yes" : "no");
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seq_printf(m, "ASEs implemented\t:%s%s%s%s\n",
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cpu_has_mips16 ? " mips16" : "",
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cpu_has_mdmx ? " mdmx" : "",
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cpu_has_mips3d ? " mips3d" : "",
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cpu_has_smartmips ? " smartmips" : "");
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sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
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cpu_has_vce ? "%u" : "not available");
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@ -4,6 +4,7 @@
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* for more details.
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*
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* Copyright (C) 2003, 2004 Ralf Baechle
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* Copyright (C) 2004 Maciej W. Rozycki
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*/
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#ifndef __ASM_CPU_FEATURES_H
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#define __ASM_CPU_FEATURES_H
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@ -39,9 +40,6 @@
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#ifndef cpu_has_watch
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#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
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#endif
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#ifndef cpu_has_mips16
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#define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16)
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#endif
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#ifndef cpu_has_divec
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#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
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#endif
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@ -66,6 +64,18 @@
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#ifndef cpu_has_llsc
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#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
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#endif
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#ifndef cpu_has_mips16
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#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
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#endif
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#ifndef cpu_has_mdmx
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#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
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#endif
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#ifndef cpu_has_mips3d
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#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
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#endif
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#ifndef cpu_has_smartmips
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#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
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#endif
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#ifndef cpu_has_vtag_icache
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#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
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#endif
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@ -7,6 +7,7 @@
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* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
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* Copyright (C) 1996 Paul M. Antoine
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2004 Maciej W. Rozycki
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*/
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#ifndef __ASM_CPU_INFO_H
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#define __ASM_CPU_INFO_H
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@ -61,6 +62,7 @@ struct cpuinfo_mips {
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* Capability and feature descriptor structure for MIPS CPU
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*/
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unsigned long options;
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unsigned long ases;
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unsigned int processor_id;
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unsigned int fpu_id;
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unsigned int cputype;
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@ -3,6 +3,7 @@
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* various MIPS cpu types.
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*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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* Copyright (C) 2004 Maciej W. Rozycki
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*/
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#ifndef _ASM_CPU_H
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#define _ASM_CPU_H
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@ -213,7 +214,6 @@
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#define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */
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#define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */
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#define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */
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#define MIPS_CPU_MIPS16 0x00000100 /* code compression */
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#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
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#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
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#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
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@ -225,4 +225,12 @@
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#define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */
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#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
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/*
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* CPU ASE encodings
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*/
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#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
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#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
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#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
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#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
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#endif /* _ASM_CPU_H */
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@ -8,7 +8,7 @@
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* Modified for further R[236]000 support by Paul M. Antoine, 1996.
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2003 Maciej W. Rozycki
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* Copyright (C) 2003, 2004 Maciej W. Rozycki
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*/
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#ifndef _ASM_MIPSREGS_H
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#define _ASM_MIPSREGS_H
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@ -477,6 +477,51 @@
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#define MIPS_CONF_AT (_ULCAST_(3) << 13)
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#define MIPS_CONF_M (_ULCAST_(1) << 31)
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/*
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* Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
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*/
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#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
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#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
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#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
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#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
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#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
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#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
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#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
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#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
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#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
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#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
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#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
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#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
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#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
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#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
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#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
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#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
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#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
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#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
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#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
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#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
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#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
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#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
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#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
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#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
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#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
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#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
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#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
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#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
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/*
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* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
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*/
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#define MIPS_FPIR_S (_ULCAST_(1) << 16)
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#define MIPS_FPIR_D (_ULCAST_(1) << 17)
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#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
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#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
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#define MIPS_FPIR_W (_ULCAST_(1) << 20)
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#define MIPS_FPIR_L (_ULCAST_(1) << 21)
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#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
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/*
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* R10000 performance counter definitions.
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*
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