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[PATCH] PCI: MSI(X) save/restore for suspend/resume
Add MSI(X) configure sapce save/restore in generic PCI helper. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Shaohua Li
Greg Kroah-Hartman
parent
f043ca43c1
commit
41017f0cac
@ -504,6 +504,201 @@ void pci_scan_msi_device(struct pci_dev *dev)
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nr_reserved_vectors++;
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}
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#ifdef CONFIG_PM
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int pci_save_msi_state(struct pci_dev *dev)
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{
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int pos, i = 0;
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u16 control;
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struct pci_cap_saved_state *save_state;
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u32 *cap;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
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if (pos <= 0 || dev->no_msi)
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return 0;
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pci_read_config_word(dev, msi_control_reg(pos), &control);
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if (!(control & PCI_MSI_FLAGS_ENABLE))
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return 0;
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save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5,
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GFP_KERNEL);
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if (!save_state) {
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printk(KERN_ERR "Out of memory in pci_save_msi_state\n");
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return -ENOMEM;
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}
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cap = &save_state->data[0];
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pci_read_config_dword(dev, pos, &cap[i++]);
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control = cap[0] >> 16;
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pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]);
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if (control & PCI_MSI_FLAGS_64BIT) {
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pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]);
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pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]);
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} else
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pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
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if (control & PCI_MSI_FLAGS_MASKBIT)
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pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
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disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
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save_state->cap_nr = PCI_CAP_ID_MSI;
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pci_add_saved_cap(dev, save_state);
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return 0;
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}
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void pci_restore_msi_state(struct pci_dev *dev)
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{
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int i = 0, pos;
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u16 control;
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struct pci_cap_saved_state *save_state;
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u32 *cap;
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save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI);
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pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
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if (!save_state || pos <= 0)
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return;
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cap = &save_state->data[0];
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control = cap[i++] >> 16;
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pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]);
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if (control & PCI_MSI_FLAGS_64BIT) {
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pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]);
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pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]);
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} else
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pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]);
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if (control & PCI_MSI_FLAGS_MASKBIT)
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pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]);
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pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
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enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
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pci_remove_saved_cap(save_state);
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kfree(save_state);
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}
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int pci_save_msix_state(struct pci_dev *dev)
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{
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int pos;
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u16 control;
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struct pci_cap_saved_state *save_state;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
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if (pos <= 0 || dev->no_msi)
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return 0;
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pci_read_config_word(dev, msi_control_reg(pos), &control);
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if (!(control & PCI_MSIX_FLAGS_ENABLE))
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return 0;
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save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16),
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GFP_KERNEL);
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if (!save_state) {
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printk(KERN_ERR "Out of memory in pci_save_msix_state\n");
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return -ENOMEM;
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}
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*((u16 *)&save_state->data[0]) = control;
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disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
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save_state->cap_nr = PCI_CAP_ID_MSIX;
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pci_add_saved_cap(dev, save_state);
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return 0;
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}
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void pci_restore_msix_state(struct pci_dev *dev)
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{
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u16 save;
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int pos;
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int vector, head, tail = 0;
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void __iomem *base;
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int j;
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struct msg_address address;
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struct msg_data data;
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struct msi_desc *entry;
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int temp;
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struct pci_cap_saved_state *save_state;
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save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX);
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if (!save_state)
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return;
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save = *((u16 *)&save_state->data[0]);
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pci_remove_saved_cap(save_state);
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kfree(save_state);
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pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
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if (pos <= 0)
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return;
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/* route the table */
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temp = dev->irq;
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if (msi_lookup_vector(dev, PCI_CAP_ID_MSIX))
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return;
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vector = head = dev->irq;
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while (head != tail) {
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entry = msi_desc[vector];
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base = entry->mask_base;
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j = entry->msi_attrib.entry_nr;
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msi_address_init(&address);
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msi_data_init(&data, vector);
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address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
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address.lo_address.value |= entry->msi_attrib.current_cpu <<
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MSI_TARGET_CPU_SHIFT;
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writel(address.lo_address.value,
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base + j * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
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writel(address.hi_address,
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base + j * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
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writel(*(u32*)&data,
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base + j * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_DATA_OFFSET);
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tail = msi_desc[vector]->link.tail;
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vector = tail;
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}
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dev->irq = temp;
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pci_write_config_word(dev, msi_control_reg(pos), save);
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enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
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}
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#endif
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static void msi_register_init(struct pci_dev *dev, struct msi_desc *entry)
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{
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struct msg_address address;
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struct msg_data data;
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int pos, vector = dev->irq;
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u16 control;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
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pci_read_config_word(dev, msi_control_reg(pos), &control);
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/* Configure MSI capability structure */
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msi_address_init(&address);
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msi_data_init(&data, vector);
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entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >>
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MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
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pci_write_config_dword(dev, msi_lower_address_reg(pos),
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address.lo_address.value);
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if (is_64bit_address(control)) {
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pci_write_config_dword(dev,
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msi_upper_address_reg(pos), address.hi_address);
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pci_write_config_word(dev,
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msi_data_reg(pos, 1), *((u32*)&data));
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} else
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pci_write_config_word(dev,
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msi_data_reg(pos, 0), *((u32*)&data));
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if (entry->msi_attrib.maskbit) {
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unsigned int maskbits, temp;
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/* All MSIs are unmasked by default, Mask them all */
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pci_read_config_dword(dev,
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msi_mask_bits_reg(pos, is_64bit_address(control)),
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&maskbits);
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temp = (1 << multi_msi_capable(control));
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temp = ((temp - 1) & ~temp);
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maskbits |= temp;
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pci_write_config_dword(dev,
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msi_mask_bits_reg(pos, is_64bit_address(control)),
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maskbits);
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}
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}
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/**
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* msi_capability_init - configure device's MSI capability structure
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* @dev: pointer to the pci_dev data structure of MSI device function
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@ -516,8 +711,6 @@ void pci_scan_msi_device(struct pci_dev *dev)
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static int msi_capability_init(struct pci_dev *dev)
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{
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struct msi_desc *entry;
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struct msg_address address;
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struct msg_data data;
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int pos, vector;
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u16 control;
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@ -549,33 +742,8 @@ static int msi_capability_init(struct pci_dev *dev)
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/* Replace with MSI handler */
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irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit);
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/* Configure MSI capability structure */
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msi_address_init(&address);
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msi_data_init(&data, vector);
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entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >>
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MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
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pci_write_config_dword(dev, msi_lower_address_reg(pos),
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address.lo_address.value);
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if (is_64bit_address(control)) {
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pci_write_config_dword(dev,
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msi_upper_address_reg(pos), address.hi_address);
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pci_write_config_word(dev,
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msi_data_reg(pos, 1), *((u32*)&data));
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} else
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pci_write_config_word(dev,
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msi_data_reg(pos, 0), *((u32*)&data));
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if (entry->msi_attrib.maskbit) {
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unsigned int maskbits, temp;
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/* All MSIs are unmasked by default, Mask them all */
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pci_read_config_dword(dev,
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msi_mask_bits_reg(pos, is_64bit_address(control)),
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&maskbits);
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temp = (1 << multi_msi_capable(control));
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temp = ((temp - 1) & ~temp);
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maskbits |= temp;
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pci_write_config_dword(dev,
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msi_mask_bits_reg(pos, is_64bit_address(control)),
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maskbits);
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}
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msi_register_init(dev, entry);
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attach_msi_entry(entry, vector);
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/* Set MSI enabled bits */
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enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
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@ -731,6 +899,7 @@ int pci_enable_msi(struct pci_dev* dev)
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vector_irq[dev->irq] = -1;
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nr_released_vectors--;
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spin_unlock_irqrestore(&msi_lock, flags);
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msi_register_init(dev, msi_desc[dev->irq]);
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enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
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return 0;
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}
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@ -444,6 +444,10 @@ pci_save_state(struct pci_dev *dev)
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/* XXX: 100% dword access ok here? */
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for (i = 0; i < 16; i++)
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pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
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if ((i = pci_save_msi_state(dev)) != 0)
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return i;
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if ((i = pci_save_msix_state(dev)) != 0)
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return i;
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return 0;
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}
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@ -458,6 +462,8 @@ pci_restore_state(struct pci_dev *dev)
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for (i = 0; i < 16; i++)
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pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]);
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pci_restore_msi_state(dev);
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pci_restore_msix_state(dev);
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return 0;
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}
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@ -55,6 +55,17 @@ void pci_no_msi(void);
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static inline void disable_msi_mode(struct pci_dev *dev, int pos, int type) { }
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static inline void pci_no_msi(void) { }
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#endif
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#if defined(CONFIG_PCI_MSI) && defined(CONFIG_PM)
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int pci_save_msi_state(struct pci_dev *dev);
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int pci_save_msix_state(struct pci_dev *dev);
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void pci_restore_msi_state(struct pci_dev *dev);
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void pci_restore_msix_state(struct pci_dev *dev);
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#else
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static inline int pci_save_msi_state(struct pci_dev *dev) { return 0; }
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static inline int pci_save_msix_state(struct pci_dev *dev) { return 0; }
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static inline void pci_restore_msi_state(struct pci_dev *dev) {}
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static inline void pci_restore_msix_state(struct pci_dev *dev) {}
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#endif
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extern int pcie_mch_quirk;
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extern struct device_attribute pci_dev_attrs[];
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@ -100,6 +100,12 @@ enum pci_bus_flags {
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PCI_BUS_FLAGS_NO_MSI = (pci_bus_flags_t) 1,
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};
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struct pci_cap_saved_state {
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struct hlist_node next;
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char cap_nr;
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u32 data[0];
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};
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/*
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* The pci_dev structure is used to describe PCI devices.
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*/
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@ -159,6 +165,7 @@ struct pci_dev {
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unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
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u32 saved_config_space[16]; /* config space saved at suspend time */
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struct hlist_head saved_cap_space;
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struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
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int rom_attr_enabled; /* has display of the rom attribute been enabled? */
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struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
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@ -169,6 +176,30 @@ struct pci_dev {
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#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
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#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
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static inline struct pci_cap_saved_state *pci_find_saved_cap(
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struct pci_dev *pci_dev,char cap)
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{
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struct pci_cap_saved_state *tmp;
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struct hlist_node *pos;
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hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
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if (tmp->cap_nr == cap)
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return tmp;
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}
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return NULL;
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}
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static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
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struct pci_cap_saved_state *new_cap)
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{
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hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
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}
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static inline void pci_remove_saved_cap(struct pci_cap_saved_state *cap)
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{
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hlist_del(&cap->next);
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}
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/*
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* For PCI devices, the region numbers are assigned this way:
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*
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