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spmi: pmic-arb: add support for HW version 5
Add support for version 5 of the SPMI PMIC arbiter. It utilizes different offsets for registers than those found on version 3. Also, the procedure to determine if writing and IRQ access is allowed for a given PPID changes for version 5. Signed-off-by: David Collins <collinsd@codeaurora.org> Signed-off-by: Kiran Gunda <kgunda@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
David Collins
Greg Kroah-Hartman
parent
000e1a43d3
commit
40f318f0ed
@ -29,6 +29,7 @@
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#define PMIC_ARB_VERSION 0x0000
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#define PMIC_ARB_VERSION_V2_MIN 0x20010000
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#define PMIC_ARB_VERSION_V3_MIN 0x30000000
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#define PMIC_ARB_VERSION_V5_MIN 0x50000000
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#define PMIC_ARB_INT_EN 0x0004
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/* PMIC Arbiter channel registers offsets */
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@ -39,7 +40,6 @@
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#define PMIC_ARB_WDATA1 0x14
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#define PMIC_ARB_RDATA0 0x18
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#define PMIC_ARB_RDATA1 0x1C
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#define PMIC_ARB_REG_APID(N) (0x800 + 0x4 * (N))
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/* Mapping Table */
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#define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N)))
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@ -52,6 +52,8 @@
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#define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */
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#define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */
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#define PMIC_ARB_APID_VALID BIT(15)
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#define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24))
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#define INVALID_EE 0xFF
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/* Ownership Table */
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#define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N)))
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@ -86,6 +88,15 @@ enum pmic_arb_cmd_op_code {
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PMIC_ARB_OP_ZERO_WRITE = 16,
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};
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/*
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* PMIC arbiter version 5 uses different register offsets for read/write vs
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* observer channels.
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*/
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enum pmic_arb_channel {
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PMIC_ARB_CHANNEL_RW,
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PMIC_ARB_CHANNEL_OBS,
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};
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/* Maximum number of support PMIC peripherals */
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#define PMIC_ARB_MAX_PERIPHS 512
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#define PMIC_ARB_TIMEOUT_US 100
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@ -112,7 +123,8 @@ struct pmic_arb_ver_ops;
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struct apid_data {
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u16 ppid;
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u8 owner;
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u8 write_ee;
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u8 irq_ee;
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};
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/**
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@ -175,12 +187,14 @@ struct spmi_pmic_arb {
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* on v2 address of SPMI_PIC_IRQ_STATUSn.
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* @irq_clear: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
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* on v2 address of SPMI_PIC_IRQ_CLEARn.
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* @apid_map_offset: offset of PMIC_ARB_REG_CHNLn
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*/
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struct pmic_arb_ver_ops {
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const char *ver_str;
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int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
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/* spmi commands (read_cmd, write_cmd, cmd) functionality */
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int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr);
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int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
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enum pmic_arb_channel ch_type);
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u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
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int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
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/* Interrupts controller functionality (offset of PIC registers) */
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@ -189,6 +203,7 @@ struct pmic_arb_ver_ops {
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void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
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void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
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void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
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u32 (*apid_map_offset)(u16 n);
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};
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static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
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@ -233,7 +248,8 @@ static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf,
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}
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static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
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void __iomem *base, u8 sid, u16 addr)
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void __iomem *base, u8 sid, u16 addr,
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enum pmic_arb_channel ch_type)
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{
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struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
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u32 status = 0;
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@ -241,7 +257,7 @@ static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
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u32 offset;
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int rc;
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rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr);
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rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type);
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if (rc < 0)
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return rc;
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@ -289,7 +305,7 @@ pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
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int rc;
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u32 offset;
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rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0);
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rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW);
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if (rc < 0)
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return rc;
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@ -298,7 +314,8 @@ pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
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raw_spin_lock_irqsave(&pmic_arb->lock, flags);
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pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
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rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0);
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rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0,
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PMIC_ARB_CHANNEL_RW);
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raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
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return rc;
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@ -334,7 +351,8 @@ static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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int rc;
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u32 offset;
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rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr);
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rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
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PMIC_ARB_CHANNEL_OBS);
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if (rc < 0)
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return rc;
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@ -359,7 +377,8 @@ static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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raw_spin_lock_irqsave(&pmic_arb->lock, flags);
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pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
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rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr);
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rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr,
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PMIC_ARB_CHANNEL_OBS);
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if (rc)
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goto done;
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@ -376,7 +395,7 @@ done:
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}
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static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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u16 addr, const u8 *buf, size_t len)
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u16 addr, const u8 *buf, size_t len)
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{
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struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
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unsigned long flags;
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@ -385,7 +404,8 @@ static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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int rc;
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u32 offset;
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rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr);
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rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
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PMIC_ARB_CHANNEL_RW);
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if (rc < 0)
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return rc;
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@ -420,7 +440,8 @@ static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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/* Start the transaction */
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pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
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rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr);
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rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr,
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PMIC_ARB_CHANNEL_RW);
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raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
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return rc;
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@ -680,12 +701,19 @@ static int qpnpint_irq_domain_dt_translate(struct irq_domain *d,
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ppid = intspec[0] << 8 | intspec[1];
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rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
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if (rc < 0) {
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dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = 0x%x, periph = 0x%x, irq = %x rc = %d\n",
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dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
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intspec[0], intspec[1], intspec[2], rc);
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return rc;
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}
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apid = rc;
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if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
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dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
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intspec[0], intspec[1], intspec[2], pmic_arb->ee,
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pmic_arb->apid_data[apid].irq_ee);
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return -ENODEV;
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}
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/* Keep track of {max,min}_apid for bounding search during interrupt */
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if (apid > pmic_arb->max_apid)
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pmic_arb->max_apid = apid;
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@ -762,7 +790,8 @@ static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
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}
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/* v1 offset per ee */
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static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr)
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static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
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enum pmic_arb_channel ch_type)
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{
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return 0x800 + 0x80 * pmic_arb->channel;
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}
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@ -773,18 +802,15 @@ static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
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u32 regval, offset;
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u16 id, apid;
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/*
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* PMIC_ARB_REG_APID is a table in HW mapping apid to ppid.
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* ppid_to_apid is an in-memory invert of that table.
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*/
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for (apid = pmic_arb->last_apid; ; apid++, apidd++) {
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offset = PMIC_ARB_REG_APID(apid);
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offset = pmic_arb->ver_ops->apid_map_offset(apid);
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if (offset >= pmic_arb->core_size)
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break;
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regval = readl_relaxed(pmic_arb->cnfg +
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SPMI_OWNERSHIP_TABLE_REG(apid));
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apidd->owner = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
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apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
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apidd->write_ee = apidd->irq_ee;
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regval = readl_relaxed(pmic_arb->core + offset);
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if (!regval)
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@ -816,8 +842,84 @@ static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
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return apid_valid & ~PMIC_ARB_APID_VALID;
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}
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static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
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{
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struct apid_data *apidd = pmic_arb->apid_data;
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struct apid_data *prev_apidd;
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u16 i, apid, ppid;
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bool valid, is_irq_ee;
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u32 regval, offset;
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/*
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* In order to allow multiple EEs to write to a single PPID in arbiter
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* version 5, there is more than one APID mapped to each PPID.
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* The owner field for each of these mappings specifies the EE which is
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* allowed to write to the APID. The owner of the last (highest) APID
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* for a given PPID will receive interrupts from the PPID.
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*/
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for (i = 0; ; i++, apidd++) {
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offset = pmic_arb->ver_ops->apid_map_offset(i);
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if (offset >= pmic_arb->core_size)
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break;
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regval = readl_relaxed(pmic_arb->core + offset);
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if (!regval)
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continue;
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ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
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is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
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regval = readl_relaxed(pmic_arb->cnfg +
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SPMI_OWNERSHIP_TABLE_REG(i));
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apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
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apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;
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valid = pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
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apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
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prev_apidd = &pmic_arb->apid_data[apid];
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if (valid && is_irq_ee &&
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prev_apidd->write_ee == pmic_arb->ee) {
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/*
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* Duplicate PPID mapping after the one for this EE;
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* override the irq owner
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*/
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prev_apidd->irq_ee = apidd->irq_ee;
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} else if (!valid || is_irq_ee) {
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/* First PPID mapping or duplicate for another EE */
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pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
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}
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apidd->ppid = ppid;
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pmic_arb->last_apid = i;
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}
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/* Dump the mapping table for debug purposes. */
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dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
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for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) {
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apid = pmic_arb->ppid_to_apid[ppid];
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if (apid & PMIC_ARB_APID_VALID) {
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apid &= ~PMIC_ARB_APID_VALID;
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apidd = &pmic_arb->apid_data[apid];
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dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n",
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ppid, apid, apidd->write_ee, apidd->irq_ee);
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}
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}
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return 0;
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}
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static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 ppid)
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{
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if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
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return -ENODEV;
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return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
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}
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/* v2 offset per ppid and per ee */
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static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr)
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static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
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enum pmic_arb_channel ch_type)
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{
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u16 apid;
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u16 ppid;
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@ -832,6 +934,35 @@ static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr)
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return 0x1000 * pmic_arb->ee + 0x8000 * apid;
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}
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/*
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* v5 offset per ee and per apid for observer channels and per apid for
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* read/write channels.
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*/
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static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
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enum pmic_arb_channel ch_type)
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{
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u16 apid;
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int rc;
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u32 offset = 0;
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u16 ppid = (sid << 8) | (addr >> 8);
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rc = pmic_arb_ppid_to_apid_v5(pmic_arb, ppid);
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if (rc < 0)
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return rc;
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apid = rc;
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switch (ch_type) {
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case PMIC_ARB_CHANNEL_OBS:
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offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
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break;
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case PMIC_ARB_CHANNEL_RW:
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offset = 0x10000 * apid;
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break;
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}
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return offset;
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}
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static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
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{
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return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
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@ -860,6 +991,12 @@ pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
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return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n;
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}
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static void __iomem *
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pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
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{
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return pmic_arb->intr + 0x10000 * m + 0x4 * n;
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}
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static void __iomem *
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pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
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{
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@ -872,6 +1009,12 @@ pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
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return pmic_arb->intr + 0x1000 * n;
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}
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static void __iomem *
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pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
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{
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return pmic_arb->wr_base + 0x100 + 0x10000 * n;
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}
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static void __iomem *
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pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
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{
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@ -884,6 +1027,12 @@ pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
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return pmic_arb->intr + 0x4 + 0x1000 * n;
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}
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static void __iomem *
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pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
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{
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return pmic_arb->wr_base + 0x104 + 0x10000 * n;
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}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
|
||||
{
|
||||
@ -896,6 +1045,22 @@ pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
|
||||
return pmic_arb->intr + 0x8 + 0x1000 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
|
||||
{
|
||||
return pmic_arb->wr_base + 0x108 + 0x10000 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_apid_map_offset_v2(u16 n)
|
||||
{
|
||||
return 0x800 + 0x4 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_apid_map_offset_v5(u16 n)
|
||||
{
|
||||
return 0x900 + 0x4 * n;
|
||||
}
|
||||
|
||||
static const struct pmic_arb_ver_ops pmic_arb_v1 = {
|
||||
.ver_str = "v1",
|
||||
.ppid_to_apid = pmic_arb_ppid_to_apid_v1,
|
||||
@ -906,6 +1071,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v1 = {
|
||||
.acc_enable = pmic_arb_acc_enable_v1,
|
||||
.irq_status = pmic_arb_irq_status_v1,
|
||||
.irq_clear = pmic_arb_irq_clear_v1,
|
||||
.apid_map_offset = pmic_arb_apid_map_offset_v2,
|
||||
};
|
||||
|
||||
static const struct pmic_arb_ver_ops pmic_arb_v2 = {
|
||||
@ -918,6 +1084,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v2 = {
|
||||
.acc_enable = pmic_arb_acc_enable_v2,
|
||||
.irq_status = pmic_arb_irq_status_v2,
|
||||
.irq_clear = pmic_arb_irq_clear_v2,
|
||||
.apid_map_offset = pmic_arb_apid_map_offset_v2,
|
||||
};
|
||||
|
||||
static const struct pmic_arb_ver_ops pmic_arb_v3 = {
|
||||
@ -930,6 +1097,20 @@ static const struct pmic_arb_ver_ops pmic_arb_v3 = {
|
||||
.acc_enable = pmic_arb_acc_enable_v2,
|
||||
.irq_status = pmic_arb_irq_status_v2,
|
||||
.irq_clear = pmic_arb_irq_clear_v2,
|
||||
.apid_map_offset = pmic_arb_apid_map_offset_v2,
|
||||
};
|
||||
|
||||
static const struct pmic_arb_ver_ops pmic_arb_v5 = {
|
||||
.ver_str = "v5",
|
||||
.ppid_to_apid = pmic_arb_ppid_to_apid_v5,
|
||||
.non_data_cmd = pmic_arb_non_data_cmd_v2,
|
||||
.offset = pmic_arb_offset_v5,
|
||||
.fmt_cmd = pmic_arb_fmt_cmd_v2,
|
||||
.owner_acc_status = pmic_arb_owner_acc_status_v5,
|
||||
.acc_enable = pmic_arb_acc_enable_v5,
|
||||
.irq_status = pmic_arb_irq_status_v5,
|
||||
.irq_clear = pmic_arb_irq_clear_v5,
|
||||
.apid_map_offset = pmic_arb_apid_map_offset_v5,
|
||||
};
|
||||
|
||||
static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
|
||||
@ -982,8 +1163,10 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
||||
|
||||
if (hw_ver < PMIC_ARB_VERSION_V3_MIN)
|
||||
pmic_arb->ver_ops = &pmic_arb_v2;
|
||||
else
|
||||
else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
|
||||
pmic_arb->ver_ops = &pmic_arb_v3;
|
||||
else
|
||||
pmic_arb->ver_ops = &pmic_arb_v5;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"obsrvr");
|
||||
@ -1073,6 +1256,15 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
||||
ctrl->read_cmd = pmic_arb_read_cmd;
|
||||
ctrl->write_cmd = pmic_arb_write_cmd;
|
||||
|
||||
if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
|
||||
err = pmic_arb_read_apid_map_v5(pmic_arb);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc= %d\n",
|
||||
err);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
}
|
||||
|
||||
dev_dbg(&pdev->dev, "adding irq domain\n");
|
||||
pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
|
||||
&pmic_arb_irq_domain_ops, pmic_arb);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user