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drm/radeon/kms: fix CS alignment checking for tiling (v2)
Covers depth, cb, and textures. Hopefully I got this right.
v2: - fix bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=28327
https://bugs.freedesktop.org/show_bug.cgi?id=28381
- use ALIGNED(), IS_ALIGNED() macros
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
7f81337720
commit
40e2a5c15d
@ -25,6 +25,7 @@
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/kernel.h>
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#include "drmP.h"
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#include "radeon.h"
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#include "r600d.h"
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@ -166,7 +167,7 @@ static void r600_cs_track_init(struct r600_cs_track *track)
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static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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{
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struct r600_cs_track *track = p->track;
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u32 bpe = 0, pitch, slice_tile_max, size, tmp, height;
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u32 bpe = 0, pitch, slice_tile_max, size, tmp, height, pitch_align;
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volatile u32 *ib = p->ib->ptr;
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if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
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@ -180,56 +181,57 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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i, track->cb_color_info[i]);
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return -EINVAL;
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}
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pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) << 3;
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/* pitch is the number of 8x8 tiles per row */
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pitch = G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1;
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slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
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if (!pitch) {
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dev_warn(p->dev, "%s:%d cb pitch (%d) for %d invalid (0x%08X)\n",
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__func__, __LINE__, pitch, i, track->cb_color_size[i]);
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return -EINVAL;
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}
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height = size / (pitch * bpe);
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height = size / (pitch * 8 * bpe);
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if (height > 8192)
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height = 8192;
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if (height > 7)
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height &= ~0x7;
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switch (G_0280A0_ARRAY_MODE(track->cb_color_info[i])) {
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case V_0280A0_ARRAY_LINEAR_GENERAL:
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/* technically height & 0x7 */
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break;
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case V_0280A0_ARRAY_LINEAR_ALIGNED:
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if (pitch & 0x3f) {
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dev_warn(p->dev, "%s:%d cb pitch (%d x %d = %d) invalid\n",
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__func__, __LINE__, pitch, bpe, pitch * bpe);
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return -EINVAL;
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}
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if ((pitch * bpe) & (track->group_size - 1)) {
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pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
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if (!IS_ALIGNED(pitch, pitch_align)) {
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dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
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__func__, __LINE__, pitch);
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return -EINVAL;
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}
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if (!IS_ALIGNED(height, 8)) {
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dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
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__func__, __LINE__, height);
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return -EINVAL;
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}
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break;
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case V_0280A0_ARRAY_1D_TILED_THIN1:
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if ((pitch * 8 * bpe * track->nsamples) & (track->group_size - 1)) {
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pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe * track->nsamples))) / 8;
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if (!IS_ALIGNED(pitch, pitch_align)) {
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dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
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__func__, __LINE__, pitch);
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return -EINVAL;
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}
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height &= ~0x7;
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if (!height)
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height = 8;
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if (!IS_ALIGNED(height, 8)) {
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dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
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__func__, __LINE__, height);
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return -EINVAL;
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}
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break;
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case V_0280A0_ARRAY_2D_TILED_THIN1:
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if (pitch & ((8 * track->nbanks) - 1)) {
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pitch_align = max((u32)track->nbanks,
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(u32)(((track->group_size / 8) / (bpe * track->nsamples)) * track->nbanks));
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if (!IS_ALIGNED(pitch, pitch_align)) {
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dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
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__func__, __LINE__, pitch);
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return -EINVAL;
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}
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tmp = pitch * 8 * bpe * track->nsamples;
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tmp = tmp / track->nbanks;
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if (tmp & (track->group_size - 1)) {
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dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
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__func__, __LINE__, pitch);
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if (!IS_ALIGNED((height / 8), track->nbanks)) {
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dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
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__func__, __LINE__, height);
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return -EINVAL;
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}
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height &= ~((16 * track->npipes) - 1);
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if (!height)
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height = 16 * track->npipes;
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break;
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default:
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dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
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@ -238,16 +240,20 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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return -EINVAL;
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}
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/* check offset */
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tmp = height * pitch;
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tmp = height * pitch * 8 * bpe;
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if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
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dev_warn(p->dev, "%s offset[%d] %d to big\n", __func__, i, track->cb_color_bo_offset[i]);
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dev_warn(p->dev, "%s offset[%d] %d too big\n", __func__, i, track->cb_color_bo_offset[i]);
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return -EINVAL;
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}
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if (!IS_ALIGNED(track->cb_color_bo_offset[i], track->group_size)) {
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dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->cb_color_bo_offset[i]);
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return -EINVAL;
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}
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/* limit max tile */
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tmp = (height * pitch) >> 6;
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tmp = (height * pitch * 8) >> 6;
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if (tmp < slice_tile_max)
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slice_tile_max = tmp;
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tmp = S_028060_PITCH_TILE_MAX((pitch >> 3) - 1) |
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tmp = S_028060_PITCH_TILE_MAX(pitch - 1) |
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S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
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ib[track->cb_color_size_idx[i]] = tmp;
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return 0;
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@ -289,7 +295,7 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
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/* Check depth buffer */
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if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
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G_028800_Z_ENABLE(track->db_depth_control)) {
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u32 nviews, bpe, ntiles;
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u32 nviews, bpe, ntiles, pitch, pitch_align, height, size;
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if (track->db_bo == NULL) {
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dev_warn(p->dev, "z/stencil with no depth buffer\n");
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return -EINVAL;
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@ -332,6 +338,51 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
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}
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ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
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} else {
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size = radeon_bo_size(track->db_bo);
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pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1;
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height = size / (pitch * 8 * bpe);
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height &= ~0x7;
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if (!height)
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height = 8;
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switch (G_028010_ARRAY_MODE(track->db_depth_info)) {
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case V_028010_ARRAY_1D_TILED_THIN1:
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pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8);
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if (!IS_ALIGNED(pitch, pitch_align)) {
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dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
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__func__, __LINE__, pitch);
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return -EINVAL;
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}
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if (!IS_ALIGNED(height, 8)) {
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dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
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__func__, __LINE__, height);
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return -EINVAL;
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}
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break;
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case V_028010_ARRAY_2D_TILED_THIN1:
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pitch_align = max((u32)track->nbanks,
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(u32)(((track->group_size / 8) / bpe) * track->nbanks));
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if (!IS_ALIGNED(pitch, pitch_align)) {
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dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
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__func__, __LINE__, pitch);
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return -EINVAL;
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}
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if ((height / 8) & (track->nbanks - 1)) {
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dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
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__func__, __LINE__, height);
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return -EINVAL;
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}
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break;
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default:
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dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
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G_028010_ARRAY_MODE(track->db_depth_info),
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track->db_depth_info);
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return -EINVAL;
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}
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if (!IS_ALIGNED(track->db_offset, track->group_size)) {
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dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->db_offset);
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return -EINVAL;
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}
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ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
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nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
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tmp = ntiles * bpe * 64 * nviews;
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@ -983,6 +1034,7 @@ static inline unsigned minify(unsigned size, unsigned levels)
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static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels,
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unsigned w0, unsigned h0, unsigned d0, unsigned bpe,
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unsigned pitch_align,
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unsigned *l0_size, unsigned *mipmap_size)
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{
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unsigned offset, i, level, face;
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@ -996,13 +1048,13 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels
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height = minify(h0, i);
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depth = minify(d0, i);
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for(face = 0; face < nfaces; face++) {
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rowstride = ((width * bpe) + 255) & ~255;
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rowstride = ALIGN((width * bpe), pitch_align);
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size = height * rowstride * depth;
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offset += size;
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offset = (offset + 0x1f) & ~0x1f;
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}
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}
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*l0_size = (((w0 * bpe) + 255) & ~255) * h0 * d0;
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*l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0;
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*mipmap_size = offset;
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if (!blevel)
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*mipmap_size -= *l0_size;
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@ -1025,8 +1077,9 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i
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struct radeon_bo *mipmap,
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u32 tiling_flags)
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{
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struct r600_cs_track *track = p->track;
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u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;
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u32 word0, word1, l0_size, mipmap_size;
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u32 word0, word1, l0_size, mipmap_size, pitch, pitch_align;
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/* on legacy kernel we don't perform advanced check */
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if (p->rdev == NULL)
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@ -1063,11 +1116,55 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i
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__func__, __LINE__, G_038004_DATA_FORMAT(word1));
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return -EINVAL;
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}
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pitch = G_038000_PITCH(word0) + 1;
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switch (G_038000_TILE_MODE(word0)) {
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case V_038000_ARRAY_LINEAR_GENERAL:
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pitch_align = 1;
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/* XXX check height align */
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break;
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case V_038000_ARRAY_LINEAR_ALIGNED:
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pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
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if (!IS_ALIGNED(pitch, pitch_align)) {
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dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
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__func__, __LINE__, pitch);
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return -EINVAL;
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}
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/* XXX check height align */
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break;
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case V_038000_ARRAY_1D_TILED_THIN1:
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pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8;
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if (!IS_ALIGNED(pitch, pitch_align)) {
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dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
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__func__, __LINE__, pitch);
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return -EINVAL;
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}
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/* XXX check height align */
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break;
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case V_038000_ARRAY_2D_TILED_THIN1:
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pitch_align = max((u32)track->nbanks,
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(u32)(((track->group_size / 8) / bpe) * track->nbanks));
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if (!IS_ALIGNED(pitch, pitch_align)) {
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dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
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__func__, __LINE__, pitch);
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return -EINVAL;
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}
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/* XXX check height align */
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break;
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default:
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dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
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G_038000_TILE_MODE(word0), word0);
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return -EINVAL;
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}
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/* XXX check offset align */
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word0 = radeon_get_ib_value(p, idx + 4);
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word1 = radeon_get_ib_value(p, idx + 5);
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blevel = G_038010_BASE_LEVEL(word0);
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nlevels = G_038014_LAST_LEVEL(word1);
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r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe, &l0_size, &mipmap_size);
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r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe,
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(pitch_align * bpe),
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&l0_size, &mipmap_size);
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/* using get ib will give us the offset into the texture bo */
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word0 = radeon_get_ib_value(p, idx + 2);
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if ((l0_size + word0) > radeon_bo_size(texture)) {
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