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tools headers: Synchoronize x86 features UAPI headers
Sync tools/arch/x86/include/asm/{cpu,disabled-,required-}features.h with
the changes in:
2961298efe ("x86/cpufeatures: Clean up Spectre v2 related CPUID flags")
20ffa1caec ("x86/speculation: Add basic IBPB (Indirect Branch Prediction Barrier) support")
5d10cbc91d ("x86/cpufeatures: Add AMD feature bits for Speculation Control")
fc67dd70ad ("x86/cpufeatures: Add Intel feature bits for Speculation Control")
95ca0ee863 ("x86/cpufeatures: Add CPUID_7_EDX CPUID leaf")
a511e79353 ("x86/intel_rdt: Enumerate L2 Code and Data Prioritization (CDP) feature")
4fdec2034b ("x86/cpufeature: Move processor tracing out of scattered features")
c995efd5a7 ("x86/retpoline: Fill RSB on context switch for affected CPUs")
76b043848f ("x86/retpoline: Add initial retpoline support")
99c6fa2511 ("x86/cpufeatures: Add X86_BUG_SPECTRE_V[12]")
de791821c2 ("x86/pti: Rename BUG_CPU_INSECURE to BUG_CPU_MELTDOWN")
6cff64b86a ("x86/mm: Use INVPCID for __native_flush_tlb_single()")
None will entail changes in the tools/perf/, synchronizing to elliminate
these perf build warnings:
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/disabled-features.h' differs from latest version at 'arch/x86/include/asm/disabled-features.h'
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/required-features.h' differs from latest version at 'arch/x86/include/asm/required-features.h'
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: David Ahern <dsahern@gmail.com>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Wang Nan <wangnan0@huawei.com>
Link: https://lkml.kernel.org/n/tip-dbdjack1k92xar5ccuq4el1h@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Arnaldo Carvalho de Melo
parent
7a16c7e15f
commit
4053717aa5
@ -13,7 +13,7 @@
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/*
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* Defines x86 CPU feature bits
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*/
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#define NCAPINTS 18 /* N 32-bit words worth of info */
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#define NCAPINTS 19 /* N 32-bit words worth of info */
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#define NBUGINTS 1 /* N 32-bit bug flags */
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/*
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@ -203,12 +203,15 @@
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
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#define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
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#define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
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#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
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#define X86_FEATURE_AVX512_4VNNIW ( 7*32+16) /* AVX-512 Neural Network Instructions */
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#define X86_FEATURE_AVX512_4FMAPS ( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */
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#define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */
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#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
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#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */
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#define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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@ -243,6 +246,7 @@
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#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
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#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
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#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
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#define X86_FEATURE_INTEL_PT ( 9*32+25) /* Intel Processor Trace */
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#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
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#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
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#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
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@ -268,6 +272,9 @@
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#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
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#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
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#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
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#define X86_FEATURE_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */
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#define X86_FEATURE_IBRS (13*32+14) /* Indirect Branch Restricted Speculation */
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#define X86_FEATURE_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */
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/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
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#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
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@ -316,6 +323,13 @@
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#define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */
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#define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
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#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
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#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
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#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
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#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
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/*
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* BUG word(s)
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*/
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@ -342,5 +356,7 @@
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#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */
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#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */
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#define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */
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#define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */
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#define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
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#endif /* _ASM_X86_CPUFEATURES_H */
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@ -77,6 +77,7 @@
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#define DISABLED_MASK15 0
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#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP)
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#define DISABLED_MASK17 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
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#define DISABLED_MASK18 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
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#endif /* _ASM_X86_DISABLED_FEATURES_H */
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@ -106,6 +106,7 @@
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#define REQUIRED_MASK15 0
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#define REQUIRED_MASK16 (NEED_LA57)
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#define REQUIRED_MASK17 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
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#define REQUIRED_MASK18 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
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#endif /* _ASM_X86_REQUIRED_FEATURES_H */
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