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drm/i915/selftests: Fix up igt_reset_engine
Now that we skip a per-engine reset on an idle engine, we need to update
the selftest to take that into account. In the process, we find that we
were not stressing the per-engine reset very hard, so add those missing
active resets.
v2: Actually test i915_reset_engine() by loading it with requests.
Fixes: f6ba181ada ("drm/i915: Skip an engine reset if it recovered before our preparations")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104313
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171217132852.30642-3-chris@chris-wilson.co.uk
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
This commit is contained in:
Chris Wilson
parent
151a99ec77
commit
3fb04cb0be
@ -132,6 +132,12 @@ static int emit_recurse_batch(struct hang *h,
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*batch++ = lower_32_bits(hws_address(hws, rq));
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*batch++ = upper_32_bits(hws_address(hws, rq));
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*batch++ = rq->fence.seqno;
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*batch++ = MI_ARB_CHECK;
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memset(batch, 0, 1024);
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batch += 1024 / sizeof(*batch);
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*batch++ = MI_ARB_CHECK;
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*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
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*batch++ = lower_32_bits(vma->node.start);
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*batch++ = upper_32_bits(vma->node.start);
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@ -140,6 +146,12 @@ static int emit_recurse_batch(struct hang *h,
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*batch++ = 0;
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*batch++ = lower_32_bits(hws_address(hws, rq));
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*batch++ = rq->fence.seqno;
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*batch++ = MI_ARB_CHECK;
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memset(batch, 0, 1024);
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batch += 1024 / sizeof(*batch);
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*batch++ = MI_ARB_CHECK;
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*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
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*batch++ = lower_32_bits(vma->node.start);
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} else if (INTEL_GEN(i915) >= 4) {
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@ -147,12 +159,24 @@ static int emit_recurse_batch(struct hang *h,
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*batch++ = 0;
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*batch++ = lower_32_bits(hws_address(hws, rq));
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*batch++ = rq->fence.seqno;
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*batch++ = MI_ARB_CHECK;
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memset(batch, 0, 1024);
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batch += 1024 / sizeof(*batch);
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*batch++ = MI_ARB_CHECK;
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*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
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*batch++ = lower_32_bits(vma->node.start);
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} else {
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*batch++ = MI_STORE_DWORD_IMM;
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*batch++ = lower_32_bits(hws_address(hws, rq));
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*batch++ = rq->fence.seqno;
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*batch++ = MI_ARB_CHECK;
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memset(batch, 0, 1024);
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batch += 1024 / sizeof(*batch);
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*batch++ = MI_ARB_CHECK;
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*batch++ = MI_BATCH_BUFFER_START | 2 << 6 | 1;
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*batch++ = lower_32_bits(vma->node.start);
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}
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@ -234,6 +258,16 @@ static void hang_fini(struct hang *h)
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i915_gem_wait_for_idle(h->i915, I915_WAIT_LOCKED);
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}
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static bool wait_for_hang(struct hang *h, struct drm_i915_gem_request *rq)
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{
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return !(wait_for_us(i915_seqno_passed(hws_seqno(h, rq),
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rq->fence.seqno),
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10) &&
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wait_for(i915_seqno_passed(hws_seqno(h, rq),
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rq->fence.seqno),
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1000));
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}
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static int igt_hang_sanitycheck(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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@ -296,6 +330,9 @@ static void global_reset_lock(struct drm_i915_private *i915)
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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pr_debug("%s: current gpu_error=%08lx\n",
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__func__, i915->gpu_error.flags);
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while (test_and_set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags))
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wait_event(i915->gpu_error.reset_queue,
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!test_bit(I915_RESET_BACKOFF,
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@ -353,54 +390,128 @@ static int igt_global_reset(void *arg)
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return err;
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}
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static int igt_reset_engine(void *arg)
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static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
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{
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struct drm_i915_private *i915 = arg;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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unsigned int reset_count, reset_engine_count;
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struct hang h;
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int err = 0;
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/* Check that we can issue a global GPU and engine reset */
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/* Check that we can issue an engine reset on an idle engine (no-op) */
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if (!intel_has_reset_engine(i915))
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return 0;
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if (active) {
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mutex_lock(&i915->drm.struct_mutex);
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err = hang_init(&h, i915);
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mutex_unlock(&i915->drm.struct_mutex);
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if (err)
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return err;
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}
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for_each_engine(engine, i915, id) {
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set_bit(I915_RESET_ENGINE + engine->id, &i915->gpu_error.flags);
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unsigned int reset_count, reset_engine_count;
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IGT_TIMEOUT(end_time);
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if (active && !intel_engine_can_store_dword(engine))
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continue;
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reset_count = i915_reset_count(&i915->gpu_error);
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reset_engine_count = i915_reset_engine_count(&i915->gpu_error,
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engine);
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err = i915_reset_engine(engine, I915_RESET_QUIET);
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if (err) {
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pr_err("i915_reset_engine failed\n");
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break;
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}
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set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
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do {
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if (active) {
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struct drm_i915_gem_request *rq;
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if (i915_reset_count(&i915->gpu_error) != reset_count) {
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pr_err("Full GPU reset recorded! (engine reset expected)\n");
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err = -EINVAL;
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break;
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}
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mutex_lock(&i915->drm.struct_mutex);
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rq = hang_create_request(&h, engine,
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i915->kernel_context);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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mutex_unlock(&i915->drm.struct_mutex);
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break;
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}
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if (i915_reset_engine_count(&i915->gpu_error, engine) ==
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reset_engine_count) {
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pr_err("No %s engine reset recorded!\n", engine->name);
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err = -EINVAL;
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break;
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}
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i915_gem_request_get(rq);
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__i915_add_request(rq, true);
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mutex_unlock(&i915->drm.struct_mutex);
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clear_bit(I915_RESET_ENGINE + engine->id,
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&i915->gpu_error.flags);
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if (!wait_for_hang(&h, rq)) {
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struct drm_printer p = drm_info_printer(i915->drm.dev);
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pr_err("%s: Failed to start request %x, at %x\n",
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__func__, rq->fence.seqno, hws_seqno(&h, rq));
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intel_engine_dump(engine, &p,
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"%s\n", engine->name);
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i915_gem_request_put(rq);
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err = -EIO;
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break;
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}
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i915_gem_request_put(rq);
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}
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engine->hangcheck.stalled = true;
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engine->hangcheck.seqno =
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intel_engine_get_seqno(engine);
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err = i915_reset_engine(engine, I915_RESET_QUIET);
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if (err) {
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pr_err("i915_reset_engine failed\n");
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break;
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}
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if (i915_reset_count(&i915->gpu_error) != reset_count) {
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pr_err("Full GPU reset recorded! (engine reset expected)\n");
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err = -EINVAL;
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break;
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}
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reset_engine_count += active;
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if (i915_reset_engine_count(&i915->gpu_error, engine) !=
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reset_engine_count) {
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pr_err("%s engine reset %srecorded!\n",
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engine->name, active ? "not " : "");
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err = -EINVAL;
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break;
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}
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engine->hangcheck.stalled = false;
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} while (time_before(jiffies, end_time));
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clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
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if (err)
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break;
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cond_resched();
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}
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if (i915_terminally_wedged(&i915->gpu_error))
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err = -EIO;
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if (active) {
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mutex_lock(&i915->drm.struct_mutex);
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hang_fini(&h);
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mutex_unlock(&i915->drm.struct_mutex);
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}
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return err;
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}
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static int igt_reset_idle_engine(void *arg)
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{
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return __igt_reset_engine(arg, false);
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}
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static int igt_reset_active_engine(void *arg)
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{
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return __igt_reset_engine(arg, true);
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}
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static int active_engine(void *data)
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{
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struct intel_engine_cs *engine = data;
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@ -462,11 +573,12 @@ err_file:
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return err;
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}
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static int igt_reset_active_engines(void *arg)
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static int __igt_reset_engine_others(struct drm_i915_private *i915,
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bool active)
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{
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struct drm_i915_private *i915 = arg;
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struct intel_engine_cs *engine, *active;
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struct intel_engine_cs *engine, *other;
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enum intel_engine_id id, tmp;
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struct hang h;
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int err = 0;
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/* Check that issuing a reset on one engine does not interfere
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@ -476,24 +588,36 @@ static int igt_reset_active_engines(void *arg)
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if (!intel_has_reset_engine(i915))
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return 0;
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if (active) {
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mutex_lock(&i915->drm.struct_mutex);
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err = hang_init(&h, i915);
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mutex_unlock(&i915->drm.struct_mutex);
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if (err)
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return err;
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}
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for_each_engine(engine, i915, id) {
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struct task_struct *threads[I915_NUM_ENGINES];
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struct task_struct *threads[I915_NUM_ENGINES] = {};
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unsigned long resets[I915_NUM_ENGINES];
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unsigned long global = i915_reset_count(&i915->gpu_error);
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unsigned long count = 0;
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IGT_TIMEOUT(end_time);
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if (active && !intel_engine_can_store_dword(engine))
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continue;
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memset(threads, 0, sizeof(threads));
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for_each_engine(active, i915, tmp) {
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for_each_engine(other, i915, tmp) {
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struct task_struct *tsk;
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if (active == engine)
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resets[tmp] = i915_reset_engine_count(&i915->gpu_error,
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other);
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if (other == engine)
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continue;
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resets[tmp] = i915_reset_engine_count(&i915->gpu_error,
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active);
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tsk = kthread_run(active_engine, active,
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"igt/%s", active->name);
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tsk = kthread_run(active_engine, other,
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"igt/%s", other->name);
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if (IS_ERR(tsk)) {
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err = PTR_ERR(tsk);
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goto unwind;
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@ -503,20 +627,70 @@ static int igt_reset_active_engines(void *arg)
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get_task_struct(tsk);
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}
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set_bit(I915_RESET_ENGINE + engine->id, &i915->gpu_error.flags);
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set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
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do {
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if (active) {
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struct drm_i915_gem_request *rq;
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mutex_lock(&i915->drm.struct_mutex);
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rq = hang_create_request(&h, engine,
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i915->kernel_context);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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mutex_unlock(&i915->drm.struct_mutex);
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break;
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}
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i915_gem_request_get(rq);
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__i915_add_request(rq, true);
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mutex_unlock(&i915->drm.struct_mutex);
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if (!wait_for_hang(&h, rq)) {
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struct drm_printer p = drm_info_printer(i915->drm.dev);
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pr_err("%s: Failed to start request %x, at %x\n",
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__func__, rq->fence.seqno, hws_seqno(&h, rq));
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intel_engine_dump(engine, &p,
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"%s\n", engine->name);
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i915_gem_request_put(rq);
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err = -EIO;
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break;
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}
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i915_gem_request_put(rq);
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}
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engine->hangcheck.stalled = true;
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engine->hangcheck.seqno =
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intel_engine_get_seqno(engine);
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err = i915_reset_engine(engine, I915_RESET_QUIET);
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if (err) {
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pr_err("i915_reset_engine(%s) failed, err=%d\n",
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engine->name, err);
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pr_err("i915_reset_engine(%s:%s) failed, err=%d\n",
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engine->name, active ? "active" : "idle", err);
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break;
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}
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engine->hangcheck.stalled = false;
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count++;
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} while (time_before(jiffies, end_time));
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clear_bit(I915_RESET_ENGINE + engine->id,
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&i915->gpu_error.flags);
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clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
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pr_info("i915_reset_engine(%s:%s): %lu resets\n",
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engine->name, active ? "active" : "idle", count);
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if (i915_reset_engine_count(&i915->gpu_error, engine) -
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resets[engine->id] != (active ? count : 0)) {
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pr_err("i915_reset_engine(%s:%s): reset %lu times, but reported %lu\n",
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engine->name, active ? "active" : "idle", count,
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i915_reset_engine_count(&i915->gpu_error,
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engine) - resets[engine->id]);
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if (!err)
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err = -EINVAL;
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}
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unwind:
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for_each_engine(active, i915, tmp) {
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for_each_engine(other, i915, tmp) {
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int ret;
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if (!threads[tmp])
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@ -524,27 +698,29 @@ unwind:
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ret = kthread_stop(threads[tmp]);
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if (ret) {
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pr_err("kthread for active engine %s failed, err=%d\n",
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active->name, ret);
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pr_err("kthread for other engine %s failed, err=%d\n",
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other->name, ret);
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if (!err)
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err = ret;
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}
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put_task_struct(threads[tmp]);
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if (resets[tmp] != i915_reset_engine_count(&i915->gpu_error,
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active)) {
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other)) {
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pr_err("Innocent engine %s was reset (count=%ld)\n",
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active->name,
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other->name,
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i915_reset_engine_count(&i915->gpu_error,
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active) - resets[tmp]);
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err = -EIO;
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other) - resets[tmp]);
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if (!err)
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err = -EINVAL;
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}
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}
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if (global != i915_reset_count(&i915->gpu_error)) {
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pr_err("Global reset (count=%ld)!\n",
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i915_reset_count(&i915->gpu_error) - global);
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err = -EIO;
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if (!err)
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err = -EINVAL;
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}
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if (err)
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@ -556,9 +732,25 @@ unwind:
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if (i915_terminally_wedged(&i915->gpu_error))
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err = -EIO;
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if (active) {
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mutex_lock(&i915->drm.struct_mutex);
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hang_fini(&h);
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mutex_unlock(&i915->drm.struct_mutex);
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}
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return err;
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}
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static int igt_reset_idle_engine_others(void *arg)
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{
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return __igt_reset_engine_others(arg, false);
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}
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static int igt_reset_active_engine_others(void *arg)
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{
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return __igt_reset_engine_others(arg, true);
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}
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static u32 fake_hangcheck(struct drm_i915_gem_request *rq)
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{
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u32 reset_count;
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@ -574,16 +766,6 @@ static u32 fake_hangcheck(struct drm_i915_gem_request *rq)
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return reset_count;
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}
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static bool wait_for_hang(struct hang *h, struct drm_i915_gem_request *rq)
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{
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return !(wait_for_us(i915_seqno_passed(hws_seqno(h, rq),
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rq->fence.seqno),
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10) &&
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wait_for(i915_seqno_passed(hws_seqno(h, rq),
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rq->fence.seqno),
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1000));
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}
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static int igt_wait_reset(void *arg)
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{
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struct drm_i915_private *i915 = arg;
|
||||
@ -617,8 +799,8 @@ static int igt_wait_reset(void *arg)
|
||||
if (!wait_for_hang(&h, rq)) {
|
||||
struct drm_printer p = drm_info_printer(i915->drm.dev);
|
||||
|
||||
pr_err("Failed to start request %x, at %x\n",
|
||||
rq->fence.seqno, hws_seqno(&h, rq));
|
||||
pr_err("%s: Failed to start request %x, at %x\n",
|
||||
__func__, rq->fence.seqno, hws_seqno(&h, rq));
|
||||
intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
|
||||
|
||||
i915_reset(i915, 0);
|
||||
@ -712,8 +894,8 @@ static int igt_reset_queue(void *arg)
|
||||
if (!wait_for_hang(&h, prev)) {
|
||||
struct drm_printer p = drm_info_printer(i915->drm.dev);
|
||||
|
||||
pr_err("Failed to start request %x, at %x\n",
|
||||
prev->fence.seqno, hws_seqno(&h, prev));
|
||||
pr_err("%s: Failed to start request %x, at %x\n",
|
||||
__func__, prev->fence.seqno, hws_seqno(&h, prev));
|
||||
intel_engine_dump(prev->engine, &p,
|
||||
"%s\n", prev->engine->name);
|
||||
|
||||
@ -819,8 +1001,8 @@ static int igt_handle_error(void *arg)
|
||||
if (!wait_for_hang(&h, rq)) {
|
||||
struct drm_printer p = drm_info_printer(i915->drm.dev);
|
||||
|
||||
pr_err("Failed to start request %x, at %x\n",
|
||||
rq->fence.seqno, hws_seqno(&h, rq));
|
||||
pr_err("%s: Failed to start request %x, at %x\n",
|
||||
__func__, rq->fence.seqno, hws_seqno(&h, rq));
|
||||
intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
|
||||
|
||||
i915_reset(i915, 0);
|
||||
@ -864,21 +1046,26 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915)
|
||||
static const struct i915_subtest tests[] = {
|
||||
SUBTEST(igt_global_reset), /* attempt to recover GPU first */
|
||||
SUBTEST(igt_hang_sanitycheck),
|
||||
SUBTEST(igt_reset_engine),
|
||||
SUBTEST(igt_reset_active_engines),
|
||||
SUBTEST(igt_reset_idle_engine),
|
||||
SUBTEST(igt_reset_active_engine),
|
||||
SUBTEST(igt_reset_idle_engine_others),
|
||||
SUBTEST(igt_reset_active_engine_others),
|
||||
SUBTEST(igt_wait_reset),
|
||||
SUBTEST(igt_reset_queue),
|
||||
SUBTEST(igt_handle_error),
|
||||
};
|
||||
bool saved_hangcheck;
|
||||
int err;
|
||||
|
||||
if (!intel_has_gpu_reset(i915))
|
||||
return 0;
|
||||
|
||||
intel_runtime_pm_get(i915);
|
||||
saved_hangcheck = fetch_and_zero(&i915_modparams.enable_hangcheck);
|
||||
|
||||
err = i915_subtests(tests, i915);
|
||||
|
||||
i915_modparams.enable_hangcheck = saved_hangcheck;
|
||||
intel_runtime_pm_put(i915);
|
||||
|
||||
return err;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user