From 3f532ef1e23395d7abb0eed316dd31123f87f448 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:14 +1000 Subject: [PATCH] drm/nouveau/dma: switch to gpuobj accessor macros Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c | 16 +++++++++------- .../gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c | 14 ++++++++------ .../gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c | 14 +++++++++----- .../gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c | 16 +++++++++------- 4 files changed, 35 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c index f5dc4f23a1b4..499a7c7e024a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c @@ -57,13 +57,15 @@ gf100_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_object *parent, ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); if (ret == 0) { - nv_wo32(*pgpuobj, 0x00, dmaobj->flags0 | nv_mclass(dmaobj)); - nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); - nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); - nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | - upper_32_bits(dmaobj->base.start)); - nv_wo32(*pgpuobj, 0x10, 0x00000000); - nv_wo32(*pgpuobj, 0x14, dmaobj->flags5); + nvkm_kmap(*pgpuobj); + nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | nv_mclass(dmaobj)); + nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); + nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); + nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | + upper_32_bits(dmaobj->base.start)); + nvkm_wo32(*pgpuobj, 0x10, 0x00000000); + nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5); + nvkm_done(*pgpuobj); } return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c index a3ea461f7f32..a28cf56454e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c @@ -63,12 +63,14 @@ gf110_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_object *parent, ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); if (ret == 0) { - nv_wo32(*pgpuobj, 0x00, dmaobj->flags0); - nv_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8); - nv_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8); - nv_wo32(*pgpuobj, 0x0c, 0x00000000); - nv_wo32(*pgpuobj, 0x10, 0x00000000); - nv_wo32(*pgpuobj, 0x14, 0x00000000); + nvkm_kmap(*pgpuobj); + nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); + nvkm_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8); + nvkm_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8); + nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); + nvkm_wo32(*pgpuobj, 0x10, 0x00000000); + nvkm_wo32(*pgpuobj, 0x14, 0x00000000); + nvkm_done(*pgpuobj); } return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c index 21c5c90b06a8..60c962bc0e47 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c @@ -64,17 +64,21 @@ nv04_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_object *parent, struct nvkm_gpuobj *pgt = mmu->vm->pgt[0].obj[0]; if (!dmaobj->base.start) return nvkm_gpuobj_dup(parent, pgt, pgpuobj); - offset = nv_ro32(pgt, 8 + (offset >> 10)); + nvkm_kmap(pgt); + offset = nvkm_ro32(pgt, 8 + (offset >> 10)); offset &= 0xfffff000; + nvkm_done(pgt); } ret = nvkm_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj); *pgpuobj = gpuobj; if (ret == 0) { - nv_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20)); - nv_wo32(*pgpuobj, 0x04, length); - nv_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset); - nv_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset); + nvkm_kmap(*pgpuobj); + nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20)); + nvkm_wo32(*pgpuobj, 0x04, length); + nvkm_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset); + nvkm_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset); + nvkm_done(*pgpuobj); } return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c index ba95f549463f..3566fa9b3ba9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c @@ -69,13 +69,15 @@ nv50_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_object *parent, ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); if (ret == 0) { - nv_wo32(*pgpuobj, 0x00, dmaobj->flags0 | nv_mclass(dmaobj)); - nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); - nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); - nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | - upper_32_bits(dmaobj->base.start)); - nv_wo32(*pgpuobj, 0x10, 0x00000000); - nv_wo32(*pgpuobj, 0x14, dmaobj->flags5); + nvkm_kmap(*pgpuobj); + nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | nv_mclass(dmaobj)); + nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); + nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); + nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | + upper_32_bits(dmaobj->base.start)); + nvkm_wo32(*pgpuobj, 0x10, 0x00000000); + nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5); + nvkm_done(*pgpuobj); } return ret;