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drm/amdkfd: report xgmi bandwidth between direct peers to the kfd
Report the min/max bandwidth in megabytes to the kfd for direct xgmi connections only. Indirect peers will report 0 since indirect route is unknown. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
331e78187f
commit
3f46c4e9ce
drivers/gpu/drm/amd
@ -553,6 +553,30 @@ uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *s
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return (uint8_t)ret;
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}
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int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct kgd_dev *dst, struct kgd_dev *src, bool is_min)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)dst, *peer_adev;
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int num_links;
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if (adev->asic_type != CHIP_ALDEBARAN)
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return 0;
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if (src)
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peer_adev = (struct amdgpu_device *)src;
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/* num links returns 0 for indirect peers since indirect route is unknown. */
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num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev);
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if (num_links < 0) {
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DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n",
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adev->gmc.xgmi.physical_node_id,
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peer_adev->gmc.xgmi.physical_node_id, num_links);
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num_links = 0;
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}
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/* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */
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return (num_links * 16 * 25000)/BITS_PER_BYTE;
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}
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uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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@ -226,6 +226,7 @@ uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd);
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uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd);
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int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd);
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uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src);
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int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct kgd_dev *dst, struct kgd_dev *src, bool is_min);
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/* Read user wptr from a specified user address space with page fault
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* disabled. The memory must be pinned and mapped to the hardware when
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@ -486,6 +486,18 @@ int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
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return -EINVAL;
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}
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int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev,
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struct amdgpu_device *peer_adev)
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{
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struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
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int i;
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for (i = 0 ; i < top->num_nodes; ++i)
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if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
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return top->nodes[i].num_links;
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return -EINVAL;
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}
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int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
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{
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struct psp_xgmi_topology_info *top_info;
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@ -59,6 +59,8 @@ int amdgpu_xgmi_remove_device(struct amdgpu_device *adev);
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int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);
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int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
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struct amdgpu_device *peer_adev);
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int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev,
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struct amdgpu_device *peer_adev);
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uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
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uint64_t addr);
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static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
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@ -1989,6 +1989,13 @@ static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size,
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sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
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sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI;
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sub_type_hdr->num_hops_xgmi = 1;
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if (adev->asic_type == CHIP_ALDEBARAN) {
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sub_type_hdr->minimum_bandwidth_mbs =
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amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(
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kdev->kgd, NULL, true);
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sub_type_hdr->maximum_bandwidth_mbs =
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sub_type_hdr->minimum_bandwidth_mbs;
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}
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} else {
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sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS;
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}
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@ -2033,6 +2040,11 @@ static int kfd_fill_gpu_xgmi_link_to_gpu(int *avail_size,
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sub_type_hdr->proximity_domain_to = proximity_domain_to;
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sub_type_hdr->num_hops_xgmi =
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amdgpu_amdkfd_get_xgmi_hops_count(kdev->kgd, peer_kdev->kgd);
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sub_type_hdr->maximum_bandwidth_mbs =
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amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(kdev->kgd, peer_kdev->kgd, false);
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sub_type_hdr->minimum_bandwidth_mbs = sub_type_hdr->maximum_bandwidth_mbs ?
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amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(kdev->kgd, NULL, true) : 0;
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return 0;
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}
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