korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-11-26 05:34:13 +08:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'cpuinit_phase2' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux

Browse Source 
Pull phase two of __cpuinit removal from Paul Gortmaker:
 "With the __cpuinit infrastructure removed earlier, this group of
  commits only removes the function/data tagging that was done with the
  various (now no-op) __cpuinit related prefixes.

  Now that the dust has settled with yesterday's v3.11-rc1, there
  hopefully shouldn't be any new users leaking back in tree, but I think
  we can leave the harmless no-op stubs there for a release as a
  courtesy to those who still have out of tree stuff and weren't paying
  attention.

  Although the commits are against the recent tag to allow for minor
  context refreshes for things like yesterday's v3.11-rc1~ slab content,
  the patches have been largely unchanged for weeks, aside from such
  trivial updates.

  For detail junkies, the largely boring and mostly irrelevant history
  of the patches can be viewed at:

    http://git.kernel.org/cgit/linux/kernel/git/paulg/cpuinit-delete.git

  If nothing else, I guess it does at least demonstrate the level of
  involvement required to shepherd such a treewide change to completion.

  This is the same repository of patches that has been applied to the
  end of the daily linux-next branches for the past several weeks"

* 'cpuinit_phase2' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux: (28 commits)
  block: delete __cpuinit usage from all block files
  drivers: delete __cpuinit usage from all remaining drivers files
  kernel: delete __cpuinit usage from all core kernel files
  rcu: delete __cpuinit usage from all rcu files
  net: delete __cpuinit usage from all net files
  acpi: delete __cpuinit usage from all acpi files
  hwmon: delete __cpuinit usage from all hwmon files
  cpufreq: delete __cpuinit usage from all cpufreq files
  clocksource+irqchip: delete __cpuinit usage from all related files
  x86: delete __cpuinit usage from all x86 files
  score: delete __cpuinit usage from all score files
  xtensa: delete __cpuinit usage from all xtensa files
  openrisc: delete __cpuinit usage from all openrisc files
  m32r: delete __cpuinit usage from all m32r files
  hexagon: delete __cpuinit usage from all hexagon files
  frv: delete __cpuinit usage from all frv files
  cris: delete __cpuinit usage from all cris files
  metag: delete __cpuinit usage from all metag files
  tile: delete __cpuinit usage from all tile files
  sh: delete __cpuinit usage from all sh files
  ...
This commit is contained in:
Linus Torvalds 2013-07-18 10:50:26 -07:00
commit 3f334c2081
333 changed files with 1079 additions and 1221 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/cpu-hotplug.txt
View File

@ -267,8 +267,8 @@ Q: If i have some kernel code that needs to be aware of CPU arrival and
A: This is what you would need in your kernel code to receive notifications.
#include <linux/cpu.h>
static int __cpuinit foobar_cpu_callback(struct notifier_block *nfb,
unsigned long action, void *hcpu)
static int foobar_cpu_callback(struct notifier_block *nfb,
unsigned long action, void *hcpu)
{
unsigned int cpu = (unsigned long)hcpu;
@ -285,7 +285,7 @@ A: This is what you would need in your kernel code to receive notifications.
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata foobar_cpu_notifer =
static struct notifier_block foobar_cpu_notifer =
{
.notifier_call = foobar_cpu_callback,
};

10
arch/alpha/kernel/smp.c
View File

@ -116,7 +116,7 @@ wait_boot_cpu_to_stop(int cpuid)
/*
* Where secondaries begin a life of C.
*/
void __cpuinit
void
smp_callin(void)
{
int cpuid = hard_smp_processor_id();
@ -194,7 +194,7 @@ wait_for_txrdy (unsigned long cpumask)
* Send a message to a secondary's console. "START" is one such
* interesting message. ;-)
*/
static void __cpuinit
static void
send_secondary_console_msg(char *str, int cpuid)
{
struct percpu_struct *cpu;
@ -285,7 +285,7 @@ recv_secondary_console_msg(void)
/*
* Convince the console to have a secondary cpu begin execution.
*/
static int __cpuinit
static int
secondary_cpu_start(int cpuid, struct task_struct *idle)
{
struct percpu_struct *cpu;
@ -356,7 +356,7 @@ secondary_cpu_start(int cpuid, struct task_struct *idle)
/*
* Bring one cpu online.
*/
static int __cpuinit
static int
smp_boot_one_cpu(int cpuid, struct task_struct *idle)
{
unsigned long timeout;
@ -472,7 +472,7 @@ smp_prepare_boot_cpu(void)
{
}
int __cpuinit
int
__cpu_up(unsigned int cpu, struct task_struct *tidle)
{
smp_boot_one_cpu(cpu, tidle);

4
arch/alpha/kernel/traps.c
View File

@ -32,7 +32,7 @@
static int opDEC_fix;
static void __cpuinit
static void
opDEC_check(void)
{
__asm__ __volatile__ (
@ -1059,7 +1059,7 @@ give_sigbus:
return;
}
void __cpuinit
void
trap_init(void)
{
/* Tell PAL-code what global pointer we want in the kernel. */

4
arch/arm/common/mcpm_platsmp.c
View File

@ -19,7 +19,7 @@
#include <asm/smp.h>
#include <asm/smp_plat.h>
static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned int mpidr, pcpu, pcluster, ret;
extern void secondary_startup(void);
@ -40,7 +40,7 @@ static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *i
return 0;
}
static void __cpuinit mcpm_secondary_init(unsigned int cpu)
static void mcpm_secondary_init(unsigned int cpu)
{
mcpm_cpu_powered_up();
}

2
arch/arm/include/asm/arch_timer.h
View File

@ -89,7 +89,7 @@ static inline u64 arch_counter_get_cntvct(void)
return cval;
}
static inline void __cpuinit arch_counter_set_user_access(void)
static inline void arch_counter_set_user_access(void)
{
u32 cntkctl;

1
arch/arm/kernel/head-common.S
View File

@ -149,7 +149,6 @@ ENDPROC(lookup_processor_type)
* r5 = proc_info pointer in physical address space
* r9 = cpuid (preserved)
*/
__CPUINIT
__lookup_processor_type:
adr r3, __lookup_processor_type_data
ldmia r3, {r4 - r6}

1
arch/arm/kernel/head-nommu.S
View File

@ -87,7 +87,6 @@ ENTRY(stext)
ENDPROC(stext)
#ifdef CONFIG_SMP
__CPUINIT
ENTRY(secondary_startup)
/*
* Common entry point for secondary CPUs.

1
arch/arm/kernel/head.S
View File

@ -343,7 +343,6 @@ __turn_mmu_on_loc:
.long __turn_mmu_on_end
#if defined(CONFIG_SMP)
__CPUINIT
ENTRY(secondary_startup)
/*
* Common entry point for secondary CPUs.

4
arch/arm/kernel/hw_breakpoint.c
View File

@ -1020,7 +1020,7 @@ out_mdbgen:
cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
}
static int __cpuinit dbg_reset_notify(struct notifier_block *self,
static int dbg_reset_notify(struct notifier_block *self,
unsigned long action, void *cpu)
{
if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
@ -1029,7 +1029,7 @@ static int __cpuinit dbg_reset_notify(struct notifier_block *self,
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata dbg_reset_nb = {
static struct notifier_block dbg_reset_nb = {
.notifier_call = dbg_reset_notify,
};

6
arch/arm/kernel/perf_event_cpu.c
View File

@ -157,8 +157,8 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
* UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
* junk values out of them.
*/
static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
unsigned long action, void *hcpu)
static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
void *hcpu)
{
if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
return NOTIFY_DONE;
@ -171,7 +171,7 @@ static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
static struct notifier_block cpu_pmu_hotplug_notifier = {
.notifier_call = cpu_pmu_notify,
};

3
arch/arm/kernel/psci_smp.c
View File

@ -46,8 +46,7 @@
extern void secondary_startup(void);
static int __cpuinit psci_boot_secondary(unsigned int cpu,
struct task_struct *idle)
static int psci_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
if (psci_ops.cpu_on)
return psci_ops.cpu_on(cpu_logical_map(cpu),

18
arch/arm/kernel/smp.c
View File

@ -58,7 +58,7 @@ struct secondary_data secondary_data;
* control for which core is the next to come out of the secondary
* boot "holding pen"
*/
volatile int __cpuinitdata pen_release = -1;
volatile int pen_release = -1;
enum ipi_msg_type {
IPI_WAKEUP,
@ -86,7 +86,7 @@ static unsigned long get_arch_pgd(pgd_t *pgd)
return pgdir >> ARCH_PGD_SHIFT;
}
int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
int __cpu_up(unsigned int cpu, struct task_struct *idle)
{
int ret;
@ -138,7 +138,7 @@ void __init smp_init_cpus(void)
smp_ops.smp_init_cpus();
}
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
int boot_secondary(unsigned int cpu, struct task_struct *idle)
{
if (smp_ops.smp_boot_secondary)
return smp_ops.smp_boot_secondary(cpu, idle);
@ -170,7 +170,7 @@ static int platform_cpu_disable(unsigned int cpu)
/*
* __cpu_disable runs on the processor to be shutdown.
*/
int __cpuinit __cpu_disable(void)
int __cpu_disable(void)
{
unsigned int cpu = smp_processor_id();
int ret;
@ -216,7 +216,7 @@ static DECLARE_COMPLETION(cpu_died);
* called on the thread which is asking for a CPU to be shutdown -
* waits until shutdown has completed, or it is timed out.
*/
void __cpuinit __cpu_die(unsigned int cpu)
void __cpu_die(unsigned int cpu)
{
if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
pr_err("CPU%u: cpu didn't die\n", cpu);
@ -306,7 +306,7 @@ void __ref cpu_die(void)
* Called by both boot and secondaries to move global data into
* per-processor storage.
*/
static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
static void smp_store_cpu_info(unsigned int cpuid)
{
struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
@ -322,7 +322,7 @@ static void percpu_timer_setup(void);
* This is the secondary CPU boot entry. We're using this CPUs
* idle thread stack, but a set of temporary page tables.
*/
asmlinkage void __cpuinit secondary_start_kernel(void)
asmlinkage void secondary_start_kernel(void)
{
struct mm_struct *mm = &init_mm;
unsigned int cpu;
@ -521,7 +521,7 @@ static void broadcast_timer_set_mode(enum clock_event_mode mode,
{
}
static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
static void broadcast_timer_setup(struct clock_event_device *evt)
{
evt->name = "dummy_timer";
evt->features = CLOCK_EVT_FEAT_ONESHOT |
@ -550,7 +550,7 @@ int local_timer_register(struct local_timer_ops *ops)
}
#endif
static void __cpuinit percpu_timer_setup(void)
static void percpu_timer_setup(void)
{
unsigned int cpu = smp_processor_id();
struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);

6
arch/arm/kernel/smp_twd.c
View File

@ -187,7 +187,7 @@ core_initcall(twd_cpufreq_init);
#endif
static void __cpuinit twd_calibrate_rate(void)
static void twd_calibrate_rate(void)
{
unsigned long count;
u64 waitjiffies;
@ -265,7 +265,7 @@ static void twd_get_clock(struct device_node *np)
/*
* Setup the local clock events for a CPU.
*/
static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
static int twd_timer_setup(struct clock_event_device *clk)
{
struct clock_event_device **this_cpu_clk;
int cpu = smp_processor_id();
@ -308,7 +308,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
return 0;
}
static struct local_timer_ops twd_lt_ops __cpuinitdata = {
static struct local_timer_ops twd_lt_ops = {
.setup = twd_timer_setup,
.stop = twd_timer_stop,
};

2
arch/arm/lib/delay.c
View File

@ -86,7 +86,7 @@ void __init register_current_timer_delay(const struct delay_timer *timer)
}
}
unsigned long __cpuinit calibrate_delay_is_known(void)
unsigned long calibrate_delay_is_known(void)
{
delay_calibrated = true;
return lpj_fine;

2
arch/arm/mach-exynos/headsmp.S
View File

@ -13,8 +13,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
/*
* exynos4 specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're

4
arch/arm/mach-exynos/platsmp.c
View File

@ -75,7 +75,7 @@ static void __iomem *scu_base_addr(void)
static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit exynos_secondary_init(unsigned int cpu)
static void exynos_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
@ -90,7 +90,7 @@ static void __cpuinit exynos_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
unsigned long phys_cpu = cpu_logical_map(cpu);

2
arch/arm/mach-highbank/platsmp.c
View File

@ -24,7 +24,7 @@
extern void secondary_startup(void);
static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
highbank_set_cpu_jump(cpu, secondary_startup);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));

2
arch/arm/mach-imx/platsmp.c
View File

@ -53,7 +53,7 @@ void imx_scu_standby_enable(void)
writel_relaxed(val, scu_base);
}
static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
imx_set_cpu_jump(cpu, v7_secondary_startup);
imx_enable_cpu(cpu, true);

2
arch/arm/mach-keystone/platsmp.c
View File

@ -21,7 +21,7 @@
#include "keystone.h"
static int __cpuinit keystone_smp_boot_secondary(unsigned int cpu,
static int keystone_smp_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
unsigned long start = virt_to_phys(&secondary_startup);

2
arch/arm/mach-msm/headsmp.S
View File

@ -11,8 +11,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
/*
* MSM specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're

6
arch/arm/mach-msm/platsmp.c
View File

@ -38,7 +38,7 @@ static inline int get_core_count(void)
return ((read_cpuid_id() >> 4) & 3) + 1;
}
static void __cpuinit msm_secondary_init(unsigned int cpu)
static void msm_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
@ -54,7 +54,7 @@ static void __cpuinit msm_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static __cpuinit void prepare_cold_cpu(unsigned int cpu)
static void prepare_cold_cpu(unsigned int cpu)
{
int ret;
ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
@ -73,7 +73,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu)
"address\n");
}
static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
static int cold_boot_done;

4
arch/arm/mach-msm/timer.c
View File

@ -139,7 +139,7 @@ static struct clocksource msm_clocksource = {
};
#ifdef CONFIG_LOCAL_TIMERS
static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
static int msm_local_timer_setup(struct clock_event_device *evt)
{
/* Use existing clock_event for cpu 0 */
if (!smp_processor_id())
@ -164,7 +164,7 @@ static void msm_local_timer_stop(struct clock_event_device *evt)
disable_percpu_irq(evt->irq);
}
static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
static struct local_timer_ops msm_local_timer_ops = {
.setup = msm_local_timer_setup,
.stop = msm_local_timer_stop,
};

2
arch/arm/mach-mvebu/coherency.c
View File

@ -28,7 +28,7 @@
#include <asm/cacheflush.h>
#include "armada-370-xp.h"
unsigned long __cpuinitdata coherency_phys_base;
unsigned long coherency_phys_base;
static void __iomem *coherency_base;
static void __iomem *coherency_cpu_base;

2
arch/arm/mach-mvebu/headsmp.S
View File

@ -21,8 +21,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
/*
* Armada XP specific entry point for secondary CPUs.
* We add the CPU to the coherency fabric and then jump to secondary

5
arch/arm/mach-mvebu/platsmp.c
View File

@ -71,13 +71,12 @@ void __init set_secondary_cpus_clock(void)
}
}
static void __cpuinit armada_xp_secondary_init(unsigned int cpu)
static void armada_xp_secondary_init(unsigned int cpu)
{
armada_xp_mpic_smp_cpu_init();
}
static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
struct task_struct *idle)
static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
pr_info("Booting CPU %d\n", cpu);

2
arch/arm/mach-omap2/omap-headsmp.S
View File

@ -20,8 +20,6 @@
#include "omap44xx.h"
__CPUINIT
/* Physical address needed since MMU not enabled yet on secondary core */
#define AUX_CORE_BOOT0_PA 0x48281800

2
arch/arm/mach-omap2/omap-mpuss-lowpower.c
View File

@ -291,7 +291,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
* @cpu : CPU ID
* @power_state: CPU low power state.
*/
int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
unsigned int cpu_state = 0;

4
arch/arm/mach-omap2/omap-smp.c
View File

@ -51,7 +51,7 @@ void __iomem *omap4_get_scu_base(void)
return scu_base;
}
static void __cpuinit omap4_secondary_init(unsigned int cpu)
static void omap4_secondary_init(unsigned int cpu)
{
/*
* Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
@ -72,7 +72,7 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
static struct clockdomain *cpu1_clkdm;
static bool booted;

4
arch/arm/mach-omap2/omap-wakeupgen.c
View File

@ -323,8 +323,8 @@ static void irq_save_secure_context(void)
#endif
#ifdef CONFIG_HOTPLUG_CPU
static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self,
unsigned long action, void *hcpu)
static int irq_cpu_hotplug_notify(struct notifier_block *self,
unsigned long action, void *hcpu)
{
unsigned int cpu = (unsigned int)hcpu;

2
arch/arm/mach-prima2/headsmp.S
View File

@ -9,8 +9,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
/*
* SIRFSOC specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're

4
arch/arm/mach-prima2/platsmp.c
View File

@ -44,7 +44,7 @@ void __init sirfsoc_map_scu(void)
scu_base = (void __iomem *)SIRFSOC_VA(base);
}
static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
static void sirfsoc_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
@ -65,7 +65,7 @@ static struct of_device_id rsc_ids[] = {
{},
};
static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
struct device_node *np;

1
arch/arm/mach-shmobile/headsmp-scu.S
View File

@ -23,7 +23,6 @@
#include <linux/init.h>
#include <asm/memory.h>
__CPUINIT
/*
* Boot code for secondary CPUs.
*

2
arch/arm/mach-shmobile/headsmp.S
View File

@ -14,8 +14,6 @@
#include <linux/init.h>
#include <asm/memory.h>
__CPUINIT
ENTRY(shmobile_invalidate_start)
bl v7_invalidate_l1
b secondary_startup

2
arch/arm/mach-shmobile/smp-emev2.c
View File

@ -30,7 +30,7 @@
#define EMEV2_SCU_BASE 0x1e000000
static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
return 0;

2
arch/arm/mach-shmobile/smp-r8a7779.c
View File

@ -81,7 +81,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
return ret ? ret : 1;
}
static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
struct r8a7779_pm_ch *ch = NULL;
int ret = -EIO;

2
arch/arm/mach-shmobile/smp-sh73a0.c
View File

@ -48,7 +48,7 @@ void __init sh73a0_register_twd(void)
}
#endif
static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
cpu = cpu_logical_map(cpu);

1
arch/arm/mach-socfpga/headsmp.S
View File

@ -10,7 +10,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
.arch armv7-a
ENTRY(secondary_trampoline)

2
arch/arm/mach-socfpga/platsmp.c
View File

@ -29,7 +29,7 @@
#include "core.h"
static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;

2
arch/arm/mach-spear/generic.h
View File

@ -37,7 +37,7 @@ void __init spear13xx_l2x0_init(void);
void spear_restart(enum reboot_mode, const char *);
void spear13xx_secondary_startup(void);
void __cpuinit spear13xx_cpu_die(unsigned int cpu);
void spear13xx_cpu_die(unsigned int cpu);
extern struct smp_operations spear13xx_smp_ops;

4
arch/arm/mach-spear/platsmp.c
View File

@ -24,7 +24,7 @@ static DEFINE_SPINLOCK(boot_lock);
static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
static void spear13xx_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
@ -40,7 +40,7 @@ static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static int __cpuinit spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;

6
arch/arm/mach-sti/platsmp.c
View File

@ -27,7 +27,7 @@
#include "smp.h"
static void __cpuinit write_pen_release(int val)
static void write_pen_release(int val)
{
pen_release = val;
smp_wmb();
@ -37,7 +37,7 @@ static void __cpuinit write_pen_release(int val)
static DEFINE_SPINLOCK(boot_lock);
void __cpuinit sti_secondary_init(unsigned int cpu)
void sti_secondary_init(unsigned int cpu)
{
trace_hardirqs_off();
@ -54,7 +54,7 @@ void __cpuinit sti_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
int __cpuinit sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;

4
arch/arm/mach-tegra/platsmp.c
View File

@ -35,7 +35,7 @@
static cpumask_t tegra_cpu_init_mask;
static void __cpuinit tegra_secondary_init(unsigned int cpu)
static void tegra_secondary_init(unsigned int cpu)
{
cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
}
@ -167,7 +167,7 @@ static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
return ret;
}
static int __cpuinit tegra_boot_secondary(unsigned int cpu,
static int tegra_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)

2
arch/arm/mach-tegra/pm.c
View File

@ -191,7 +191,7 @@ static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
[TEGRA_SUSPEND_LP0] = "LP0",
};
static int __cpuinit tegra_suspend_enter(suspend_state_t state)
static int tegra_suspend_enter(suspend_state_t state)
{
enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();

4
arch/arm/mach-ux500/platsmp.c
View File

@ -54,7 +54,7 @@ static void __iomem *scu_base_addr(void)
static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit ux500_secondary_init(unsigned int cpu)
static void ux500_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
@ -69,7 +69,7 @@ static void __cpuinit ux500_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;

2
arch/arm/mach-zynq/common.h
View File

@ -27,7 +27,7 @@ extern void secondary_startup(void);
extern char zynq_secondary_trampoline;
extern char zynq_secondary_trampoline_jump;
extern char zynq_secondary_trampoline_end;
extern int __cpuinit zynq_cpun_start(u32 address, int cpu);
extern int zynq_cpun_start(u32 address, int cpu);
extern struct smp_operations zynq_smp_ops __initdata;
#endif

2
arch/arm/mach-zynq/headsmp.S
View File

@ -9,8 +9,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
ENTRY(zynq_secondary_trampoline)
ldr r0, [pc]
bx r0

6
arch/arm/mach-zynq/platsmp.c
View File

@ -30,11 +30,11 @@
/*
* Store number of cores in the system
* Because of scu_get_core_count() must be in __init section and can't
* be called from zynq_cpun_start() because it is in __cpuinit section.
* be called from zynq_cpun_start() because it is not in __init section.
*/
static int ncores;
int __cpuinit zynq_cpun_start(u32 address, int cpu)
int zynq_cpun_start(u32 address, int cpu)
{
u32 trampoline_code_size = &zynq_secondary_trampoline_end -
&zynq_secondary_trampoline;
@ -92,7 +92,7 @@ int __cpuinit zynq_cpun_start(u32 address, int cpu)
}
EXPORT_SYMBOL(zynq_cpun_start);
static int __cpuinit zynq_boot_secondary(unsigned int cpu,
static int zynq_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);

2
arch/arm/mm/proc-arm1020.S
View File

@ -443,8 +443,6 @@ ENTRY(cpu_arm1020_set_pte_ext)
#endif /* CONFIG_MMU */
mov pc, lr
__CPUINIT
.type __arm1020_setup, #function
__arm1020_setup:
mov r0, #0

2
arch/arm/mm/proc-arm1020e.S
View File

@ -425,8 +425,6 @@ ENTRY(cpu_arm1020e_set_pte_ext)
#endif /* CONFIG_MMU */
mov pc, lr
__CPUINIT
.type __arm1020e_setup, #function
__arm1020e_setup:
mov r0, #0

2
arch/arm/mm/proc-arm1022.S
View File

@ -407,8 +407,6 @@ ENTRY(cpu_arm1022_set_pte_ext)
#endif /* CONFIG_MMU */
mov pc, lr
__CPUINIT
.type __arm1022_setup, #function
__arm1022_setup:
mov r0, #0

3
arch/arm/mm/proc-arm1026.S
View File

@ -396,9 +396,6 @@ ENTRY(cpu_arm1026_set_pte_ext)
#endif /* CONFIG_MMU */
mov pc, lr
__CPUINIT
.type __arm1026_setup, #function
__arm1026_setup:
mov r0, #0

2
arch/arm/mm/proc-arm720.S
View File

@ -116,8 +116,6 @@ ENTRY(cpu_arm720_reset)
ENDPROC(cpu_arm720_reset)
.popsection
__CPUINIT
.type __arm710_setup, #function
__arm710_setup:
mov r0, #0

2
arch/arm/mm/proc-arm740.S
View File

@ -60,8 +60,6 @@ ENTRY(cpu_arm740_reset)
ENDPROC(cpu_arm740_reset)
.popsection
__CPUINIT
.type __arm740_setup, #function
__arm740_setup:
mov r0, #0

2
arch/arm/mm/proc-arm7tdmi.S
View File

@ -51,8 +51,6 @@ ENTRY(cpu_arm7tdmi_reset)
ENDPROC(cpu_arm7tdmi_reset)
.popsection
__CPUINIT
.type __arm7tdmi_setup, #function
__arm7tdmi_setup:
mov pc, lr

2
arch/arm/mm/proc-arm920.S
View File

@ -410,8 +410,6 @@ ENTRY(cpu_arm920_do_resume)
ENDPROC(cpu_arm920_do_resume)
#endif
__CPUINIT
.type __arm920_setup, #function
__arm920_setup:
mov r0, #0

2
arch/arm/mm/proc-arm922.S
View File

@ -388,8 +388,6 @@ ENTRY(cpu_arm922_set_pte_ext)
#endif /* CONFIG_MMU */
mov pc, lr
__CPUINIT
.type __arm922_setup, #function
__arm922_setup:
mov r0, #0

2
arch/arm/mm/proc-arm925.S
View File

@ -438,8 +438,6 @@ ENTRY(cpu_arm925_set_pte_ext)
#endif /* CONFIG_MMU */
mov pc, lr
__CPUINIT
.type __arm925_setup, #function
__arm925_setup:
mov r0, #0

2
arch/arm/mm/proc-arm926.S
View File

@ -425,8 +425,6 @@ ENTRY(cpu_arm926_do_resume)
ENDPROC(cpu_arm926_do_resume)
#endif
__CPUINIT
.type __arm926_setup, #function
__arm926_setup:
mov r0, #0

2
arch/arm/mm/proc-arm940.S
View File

@ -273,8 +273,6 @@ ENDPROC(arm940_dma_unmap_area)
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions arm940
__CPUINIT
.type __arm940_setup, #function
__arm940_setup:
mov r0, #0

2
arch/arm/mm/proc-arm946.S
View File

@ -326,8 +326,6 @@ ENTRY(cpu_arm946_dcache_clean_area)
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
__CPUINIT
.type __arm946_setup, #function
__arm946_setup:
mov r0, #0

2
arch/arm/mm/proc-arm9tdmi.S
View File

@ -51,8 +51,6 @@ ENTRY(cpu_arm9tdmi_reset)
ENDPROC(cpu_arm9tdmi_reset)
.popsection
__CPUINIT
.type __arm9tdmi_setup, #function
__arm9tdmi_setup:
mov pc, lr

2
arch/arm/mm/proc-fa526.S
View File

@ -135,8 +135,6 @@ ENTRY(cpu_fa526_set_pte_ext)
#endif
mov pc, lr
__CPUINIT
.type __fa526_setup, #function
__fa526_setup:
/* On return of this routine, r0 must carry correct flags for CFG register */

2
arch/arm/mm/proc-feroceon.S
View File

@ -514,8 +514,6 @@ ENTRY(cpu_feroceon_set_pte_ext)
#endif
mov pc, lr
__CPUINIT
.type __feroceon_setup, #function
__feroceon_setup:
mov r0, #0

2
arch/arm/mm/proc-mohawk.S
View File

@ -383,8 +383,6 @@ ENTRY(cpu_mohawk_do_resume)
ENDPROC(cpu_mohawk_do_resume)
#endif
__CPUINIT
.type __mohawk_setup, #function
__mohawk_setup:
mov r0, #0

2
arch/arm/mm/proc-sa110.S
View File

@ -159,8 +159,6 @@ ENTRY(cpu_sa110_set_pte_ext)
#endif
mov pc, lr
__CPUINIT
.type __sa110_setup, #function
__sa110_setup:
mov r10, #0

2
arch/arm/mm/proc-sa1100.S
View File

@ -198,8 +198,6 @@ ENTRY(cpu_sa1100_do_resume)
ENDPROC(cpu_sa1100_do_resume)
#endif
__CPUINIT
.type __sa1100_setup, #function
__sa1100_setup:
mov r0, #0

2
arch/arm/mm/proc-v6.S
View File

@ -180,8 +180,6 @@ ENDPROC(cpu_v6_do_resume)
.align
__CPUINIT
/*
* __v6_setup
*

4
arch/arm/mm/proc-v7-2level.S
View File

@ -160,8 +160,6 @@ ENDPROC(cpu_v7_set_pte_ext)
mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
.endm
__CPUINIT
/* AT
* TFR EV X F I D LR S
* .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
@ -172,5 +170,3 @@ ENDPROC(cpu_v7_set_pte_ext)
.type v7_crval, #object
v7_crval:
crval clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
.previous

4
arch/arm/mm/proc-v7-3level.S
View File

@ -140,8 +140,6 @@ ENDPROC(cpu_v7_set_pte_ext)
mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0
.endm
__CPUINIT
/*
* AT
* TFR EV X F IHD LR S
@ -153,5 +151,3 @@ ENDPROC(cpu_v7_set_pte_ext)
.type v7_crval, #object
v7_crval:
crval clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c
.previous

2
arch/arm/mm/proc-v7.S
View File

@ -167,8 +167,6 @@ ENDPROC(cpu_pj4b_do_idle)
#endif
__CPUINIT
/*
* __v7_setup
*

2
arch/arm/mm/proc-xsc3.S
View File

@ -446,8 +446,6 @@ ENTRY(cpu_xsc3_do_resume)
ENDPROC(cpu_xsc3_do_resume)
#endif
__CPUINIT
.type __xsc3_setup, #function
__xsc3_setup:
mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE

2
arch/arm/mm/proc-xscale.S
View File

@ -558,8 +558,6 @@ ENTRY(cpu_xscale_do_resume)
ENDPROC(cpu_xscale_do_resume)
#endif
__CPUINIT
.type __xscale_setup, #function
__xscale_setup:
mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB

6
arch/arm/plat-versatile/platsmp.c
View File

@ -23,7 +23,7 @@
* observers, irrespective of whether they're taking part in coherency
* or not. This is necessary for the hotplug code to work reliably.
*/
static void __cpuinit write_pen_release(int val)
static void write_pen_release(int val)
{
pen_release = val;
smp_wmb();
@ -33,7 +33,7 @@ static void __cpuinit write_pen_release(int val)
static DEFINE_SPINLOCK(boot_lock);
void __cpuinit versatile_secondary_init(unsigned int cpu)
void versatile_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
@ -48,7 +48,7 @@ void __cpuinit versatile_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;

2
arch/arm64/include/asm/arch_timer.h
View File

@ -97,7 +97,7 @@ static inline u32 arch_timer_get_cntfrq(void)
return val;
}
static inline void __cpuinit arch_counter_set_user_access(void)
static inline void arch_counter_set_user_access(void)
{
u32 cntkctl;

6
arch/arm64/kernel/debug-monitors.c
View File

@ -141,7 +141,7 @@ static void clear_os_lock(void *unused)
isb();
}
static int __cpuinit os_lock_notify(struct notifier_block *self,
static int os_lock_notify(struct notifier_block *self,
unsigned long action, void *data)
{
int cpu = (unsigned long)data;
@ -150,11 +150,11 @@ static int __cpuinit os_lock_notify(struct notifier_block *self,
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata os_lock_nb = {
static struct notifier_block os_lock_nb = {
.notifier_call = os_lock_notify,
};
static int __cpuinit debug_monitors_init(void)
static int debug_monitors_init(void)
{
/* Clear the OS lock. */
smp_call_function(clear_os_lock, NULL, 1);

4
arch/arm64/kernel/hw_breakpoint.c
View File

@ -821,7 +821,7 @@ static void reset_ctrl_regs(void *unused)
}
}
static int __cpuinit hw_breakpoint_reset_notify(struct notifier_block *self,
static int hw_breakpoint_reset_notify(struct notifier_block *self,
unsigned long action,
void *hcpu)
{
@ -831,7 +831,7 @@ static int __cpuinit hw_breakpoint_reset_notify(struct notifier_block *self,
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata hw_breakpoint_reset_nb = {
static struct notifier_block hw_breakpoint_reset_nb = {
.notifier_call = hw_breakpoint_reset_notify,
};

8
arch/arm64/kernel/smp.c
View File

@ -71,7 +71,7 @@ static DEFINE_RAW_SPINLOCK(boot_lock);
* in coherency or not. This is necessary for the hotplug code to work
* reliably.
*/
static void __cpuinit write_pen_release(u64 val)
static void write_pen_release(u64 val)
{
void *start = (void *)&secondary_holding_pen_release;
unsigned long size = sizeof(secondary_holding_pen_release);
@ -84,7 +84,7 @@ static void __cpuinit write_pen_release(u64 val)
* Boot a secondary CPU, and assign it the specified idle task.
* This also gives us the initial stack to use for this CPU.
*/
static int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
static int boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
@ -122,7 +122,7 @@ static int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
static DECLARE_COMPLETION(cpu_running);
int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
int __cpu_up(unsigned int cpu, struct task_struct *idle)
{
int ret;
@ -162,7 +162,7 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
* This is the secondary CPU boot entry. We're using this CPUs
* idle thread stack, but a set of temporary page tables.
*/
asmlinkage void __cpuinit secondary_start_kernel(void)
asmlinkage void secondary_start_kernel(void)
{
struct mm_struct *mm = &init_mm;
unsigned int cpu = smp_processor_id();

2
arch/blackfin/kernel/perf_event.c
View File

@ -468,7 +468,7 @@ static void bfin_pmu_setup(int cpu)
memset(cpuhw, 0, sizeof(struct cpu_hw_events));
}
static int __cpuinit
static int
bfin_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
{
unsigned int cpu = (long)hcpu;

4
arch/blackfin/kernel/setup.c
View File

@ -99,7 +99,7 @@ void __init generate_cplb_tables(void)
}
#endif
void __cpuinit bfin_setup_caches(unsigned int cpu)
void bfin_setup_caches(unsigned int cpu)
{
#ifdef CONFIG_BFIN_ICACHE
bfin_icache_init(icplb_tbl[cpu]);
@ -165,7 +165,7 @@ void __cpuinit bfin_setup_caches(unsigned int cpu)
#endif
}
void __cpuinit bfin_setup_cpudata(unsigned int cpu)
void bfin_setup_cpudata(unsigned int cpu)
{
struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);

6
arch/blackfin/mach-bf561/smp.c
View File

@ -48,7 +48,7 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
return -EINVAL;
}
void __cpuinit platform_secondary_init(unsigned int cpu)
void platform_secondary_init(unsigned int cpu)
{
/* Clone setup for peripheral interrupt sources from CoreA. */
bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
@ -73,7 +73,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
int platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
@ -154,7 +154,7 @@ void platform_clear_ipi(unsigned int cpu, int irq)
* Setup core B's local core timer.
* In SMP, core timer is used for clock event device.
*/
void __cpuinit bfin_local_timer_setup(void)
void bfin_local_timer_setup(void)
{
#if defined(CONFIG_TICKSOURCE_CORETMR)
struct irq_data *data = irq_get_irq_data(IRQ_CORETMR);

4
arch/blackfin/mach-common/cache-c.c
View File

@ -52,7 +52,7 @@ bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
}
#ifdef CONFIG_BFIN_ICACHE
void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
void bfin_icache_init(struct cplb_entry *icplb_tbl)
{
bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
(IMC | ENICPLB));
@ -60,7 +60,7 @@ void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
#endif
#ifdef CONFIG_BFIN_DCACHE
void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
void bfin_dcache_init(struct cplb_entry *dcplb_tbl)
{
/*
* Anomaly notes:

2
arch/blackfin/mach-common/ints-priority.c
View File

@ -1281,7 +1281,7 @@ static struct irq_chip bfin_gpio_irqchip = {
.irq_set_wake = bfin_gpio_set_wake,
};
void __cpuinit init_exception_vectors(void)
void init_exception_vectors(void)
{
/* cannot program in software:
* evt0 - emulation (jtag)

12
arch/blackfin/mach-common/smp.c
View File

@ -46,7 +46,7 @@ struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
unsigned long blackfin_iflush_l1_entry[NR_CPUS];
#endif
struct blackfin_initial_pda __cpuinitdata initial_pda_coreb;
struct blackfin_initial_pda initial_pda_coreb;
enum ipi_message_type {
BFIN_IPI_NONE,
@ -246,7 +246,7 @@ void smp_send_stop(void)
return;
}
int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
int __cpu_up(unsigned int cpu, struct task_struct *idle)
{
int ret;
@ -259,7 +259,7 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
return ret;
}
static void __cpuinit setup_secondary(unsigned int cpu)
static void setup_secondary(unsigned int cpu)
{
unsigned long ilat;
@ -277,7 +277,7 @@ static void __cpuinit setup_secondary(unsigned int cpu)
IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
}
void __cpuinit secondary_start_kernel(void)
void secondary_start_kernel(void)
{
unsigned int cpu = smp_processor_id();
struct mm_struct *mm = &init_mm;
@ -402,7 +402,7 @@ EXPORT_SYMBOL(resync_core_dcache);
#endif
#ifdef CONFIG_HOTPLUG_CPU
int __cpuexit __cpu_disable(void)
int __cpu_disable(void)
{
unsigned int cpu = smp_processor_id();
@ -415,7 +415,7 @@ int __cpuexit __cpu_disable(void)
static DECLARE_COMPLETION(cpu_killed);
int __cpuexit __cpu_die(unsigned int cpu)
int __cpu_die(unsigned int cpu)
{
return wait_for_completion_timeout(&cpu_killed, 5000);
}

2
arch/cris/arch-v32/kernel/smp.c
View File

@ -197,7 +197,7 @@ int setup_profiling_timer(unsigned int multiplier)
*/
unsigned long cache_decay_ticks = 1;
int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
int __cpu_up(unsigned int cpu, struct task_struct *tidle)
{
smp_boot_one_cpu(cpu, tidle);
return cpu_online(cpu) ? 0 : -ENOSYS;

2
arch/frv/kernel/setup.c
View File

@ -709,7 +709,7 @@ static void __init reserve_dma_coherent(void)
/*
* calibrate the delay loop
*/
void __cpuinit calibrate_delay(void)
void calibrate_delay(void)
{
loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ);

2
arch/hexagon/kernel/setup.c
View File

@ -41,7 +41,7 @@ static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
int on_simulator;
void __cpuinit calibrate_delay(void)
void calibrate_delay(void)
{
loops_per_jiffy = thread_freq_mhz * 1000000 / HZ;
}

4
arch/hexagon/kernel/smp.c
View File

@ -146,7 +146,7 @@ void __init smp_prepare_boot_cpu(void)
* to point to current thread info
*/
void __cpuinit start_secondary(void)
void start_secondary(void)
{
unsigned int cpu;
unsigned long thread_ptr;
@ -194,7 +194,7 @@ void __cpuinit start_secondary(void)
* maintains control until "cpu_online(cpu)" is set.
*/
int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
int __cpu_up(unsigned int cpu, struct task_struct *idle)
{
struct thread_info *thread = (struct thread_info *)idle->stack;
void *stack_start;

2
arch/m32r/kernel/smpboot.c
View File

@ -343,7 +343,7 @@ static void __init do_boot_cpu(int phys_id)
}
}
int __cpuinit __cpu_up(unsigned int cpu_id, struct task_struct *tidle)
int __cpu_up(unsigned int cpu_id, struct task_struct *tidle)
{
int timeout;

6
arch/metag/kernel/perf/perf_event.c
View File

@ -813,8 +813,8 @@ static struct metag_pmu _metag_pmu = {
};
/* PMU CPU hotplug notifier */
static int __cpuinit metag_pmu_cpu_notify(struct notifier_block *b,
unsigned long action, void *hcpu)
static int metag_pmu_cpu_notify(struct notifier_block *b, unsigned long action,
void *hcpu)
{
unsigned int cpu = (unsigned int)hcpu;
struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
@ -828,7 +828,7 @@ static int __cpuinit metag_pmu_cpu_notify(struct notifier_block *b,
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata metag_pmu_notifier = {
static struct notifier_block metag_pmu_notifier = {
.notifier_call = metag_pmu_cpu_notify,
};

22
arch/metag/kernel/smp.c
View File

@ -68,7 +68,7 @@ static DECLARE_COMPLETION(cpu_running);
/*
* "thread" is assumed to be a valid Meta hardware thread ID.
*/
int __cpuinit boot_secondary(unsigned int thread, struct task_struct *idle)
int boot_secondary(unsigned int thread, struct task_struct *idle)
{
u32 val;
@ -118,11 +118,9 @@ int __cpuinit boot_secondary(unsigned int thread, struct task_struct *idle)
* If the cache partition has changed, prints a message to the log describing
* those changes.
*/
static __cpuinit void describe_cachepart_change(unsigned int thread,
const char *label,
unsigned int sz,
unsigned int old,
unsigned int new)
static void describe_cachepart_change(unsigned int thread, const char *label,
unsigned int sz, unsigned int old,
unsigned int new)
{
unsigned int lor1, land1, gor1, gand1;
unsigned int lor2, land2, gor2, gand2;
@ -170,7 +168,7 @@ static __cpuinit void describe_cachepart_change(unsigned int thread,
* Ensures that coherency is enabled and that the threads share the same cache
* partitions.
*/
static __cpuinit void setup_smp_cache(unsigned int thread)
static void setup_smp_cache(unsigned int thread)
{
unsigned int this_thread, lflags;
unsigned int dcsz, dcpart_this, dcpart_old, dcpart_new;
@ -215,7 +213,7 @@ static __cpuinit void setup_smp_cache(unsigned int thread)
icpart_old, icpart_new);
}
int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
int __cpu_up(unsigned int cpu, struct task_struct *idle)
{
unsigned int thread = cpu_2_hwthread_id[cpu];
int ret;
@ -268,7 +266,7 @@ static DECLARE_COMPLETION(cpu_killed);
/*
* __cpu_disable runs on the processor to be shutdown.
*/
int __cpuexit __cpu_disable(void)
int __cpu_disable(void)
{
unsigned int cpu = smp_processor_id();
@ -299,7 +297,7 @@ int __cpuexit __cpu_disable(void)
* called on the thread which is asking for a CPU to be shutdown -
* waits until shutdown has completed, or it is timed out.
*/
void __cpuexit __cpu_die(unsigned int cpu)
void __cpu_die(unsigned int cpu)
{
if (!wait_for_completion_timeout(&cpu_killed, msecs_to_jiffies(1)))
pr_err("CPU%u: unable to kill\n", cpu);
@ -311,7 +309,7 @@ void __cpuexit __cpu_die(unsigned int cpu)
* Note that we do not return from this function. If this cpu is
* brought online again it will need to run secondary_startup().
*/
void __cpuexit cpu_die(void)
void cpu_die(void)
{
local_irq_disable();
idle_task_exit();
@ -326,7 +324,7 @@ void __cpuexit cpu_die(void)
* Called by both boot and secondaries to move global data into
* per-processor storage.
*/
void __cpuinit smp_store_cpu_info(unsigned int cpuid)
void smp_store_cpu_info(unsigned int cpuid)
{
struct cpuinfo_metag *cpu_info = &per_cpu(cpu_data, cpuid);

2
arch/metag/kernel/traps.c
View File

@ -812,7 +812,7 @@ static void set_trigger_mask(unsigned int mask)
}
#endif
void __cpuinit per_cpu_trap_init(unsigned long cpu)
void per_cpu_trap_init(unsigned long cpu)
{
TBIRES int_context;
unsigned int thread = cpu_2_hwthread_id[cpu];

2
arch/mips/ath79/setup.c
View File

@ -182,7 +182,7 @@ const char *get_system_type(void)
return ath79_sys_type;
}
unsigned int __cpuinit get_c0_compare_int(void)
unsigned int get_c0_compare_int(void)
{
return CP0_LEGACY_COMPARE_IRQ;
}

12
arch/mips/cavium-octeon/octeon-irq.c
View File

@ -1095,7 +1095,7 @@ static void octeon_irq_ip3_ciu(void)
static bool octeon_irq_use_ip4;
static void __cpuinit octeon_irq_local_enable_ip4(void *arg)
static void octeon_irq_local_enable_ip4(void *arg)
{
set_c0_status(STATUSF_IP4);
}
@ -1110,21 +1110,21 @@ static void (*octeon_irq_ip2)(void);
static void (*octeon_irq_ip3)(void);
static void (*octeon_irq_ip4)(void);
void __cpuinitdata (*octeon_irq_setup_secondary)(void);
void (*octeon_irq_setup_secondary)(void);
void __cpuinit octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t h)
void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t h)
{
octeon_irq_ip4 = h;
octeon_irq_use_ip4 = true;
on_each_cpu(octeon_irq_local_enable_ip4, NULL, 1);
}
static void __cpuinit octeon_irq_percpu_enable(void)
static void octeon_irq_percpu_enable(void)
{
irq_cpu_online();
}
static void __cpuinit octeon_irq_init_ciu_percpu(void)
static void octeon_irq_init_ciu_percpu(void)
{
int coreid = cvmx_get_core_num();
@ -1167,7 +1167,7 @@ static void octeon_irq_init_ciu2_percpu(void)
cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid));
}
static void __cpuinit octeon_irq_setup_secondary_ciu(void)
static void octeon_irq_setup_secondary_ciu(void)
{
octeon_irq_init_ciu_percpu();
octeon_irq_percpu_enable();

6
arch/mips/cavium-octeon/smp.c
View File

@ -173,7 +173,7 @@ static void octeon_boot_secondary(int cpu, struct task_struct *idle)
* After we've done initial boot, this function is called to allow the
* board code to clean up state, if needed
*/
static void __cpuinit octeon_init_secondary(void)
static void octeon_init_secondary(void)
{
unsigned int sr;
@ -375,7 +375,7 @@ static int octeon_update_boot_vector(unsigned int cpu)
return 0;
}
static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
static int octeon_cpu_callback(struct notifier_block *nfb,
unsigned long action, void *hcpu)
{
unsigned int cpu = (unsigned long)hcpu;
@ -394,7 +394,7 @@ static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
return NOTIFY_OK;
}
static int __cpuinit register_cavium_notifier(void)
static int register_cavium_notifier(void)
{
hotcpu_notifier(octeon_cpu_callback, 0);
return 0;

37
arch/mips/include/asm/uasm.h
View File

@ -13,12 +13,8 @@
#ifdef CONFIG_EXPORT_UASM
#include <linux/export.h>
#define __uasminit
#define __uasminitdata
#define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym)
#else
#define __uasminit __cpuinit
#define __uasminitdata __cpuinitdata
#define UASM_EXPORT_SYMBOL(sym)
#endif
@ -54,43 +50,36 @@
#endif
#define Ip_u1u2u3(op) \
void __uasminit \
ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
#define Ip_u2u1u3(op) \
void __uasminit \
ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
#define Ip_u3u1u2(op) \
void __uasminit \
ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
#define Ip_u1u2s3(op) \
void __uasminit \
ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
#define Ip_u2s3u1(op) \
void __uasminit \
ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c)
void ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c)
#define Ip_u2u1s3(op) \
void __uasminit \
ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
#define Ip_u2u1msbu3(op) \
void __uasminit \
ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
unsigned int d)
#define Ip_u1u2(op) \
void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b)
void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b)
#define Ip_u1s2(op) \
void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, signed int b)
void ISAOPC(op)(u32 **buf, unsigned int a, signed int b)
#define Ip_u1(op) void __uasminit ISAOPC(op)(u32 **buf, unsigned int a)
#define Ip_u1(op) void ISAOPC(op)(u32 **buf, unsigned int a)
#define Ip_0(op) void __uasminit ISAOPC(op)(u32 **buf)
#define Ip_0(op) void ISAOPC(op)(u32 **buf)
Ip_u2u1s3(_addiu);
Ip_u3u1u2(_addu);
@ -163,7 +152,7 @@ struct uasm_label {
int lab;
};
void __uasminit ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr,
void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr,
int lid);
#ifdef CONFIG_64BIT
int ISAFUNC(uasm_in_compat_space_p)(long addr);
@ -174,7 +163,7 @@ void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr);
void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr);
#define UASM_L_LA(lb) \
static inline void __uasminit ISAFUNC(uasm_l##lb)(struct uasm_label **lab, u32 *addr) \
static inline void ISAFUNC(uasm_l##lb)(struct uasm_label **lab, u32 *addr) \
{ \
ISAFUNC(uasm_build_label)(lab, addr, label##lb); \
}

4
arch/mips/kernel/bmips_vec.S
View File

@ -28,8 +28,6 @@
.set mips0
.endm
__CPUINIT
/***********************************************************************
* Alternate CPU1 startup vector for BMIPS4350
*
@ -216,8 +214,6 @@ END(bmips_smp_int_vec)
* Certain CPUs support extending kseg0 to 1024MB.
***********************************************************************/
__CPUINIT
LEAF(bmips_enable_xks01)
#if defined(CONFIG_XKS01)

2
arch/mips/kernel/cevt-bcm1480.c
View File

@ -109,7 +109,7 @@ static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
void __cpuinit sb1480_clockevent_init(void)
void sb1480_clockevent_init(void)
{
unsigned int cpu = smp_processor_id();
unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;

2
arch/mips/kernel/cevt-gic.c
View File

@ -59,7 +59,7 @@ void gic_event_handler(struct clock_event_device *dev)
{
}
int __cpuinit gic_clockevent_init(void)
int gic_clockevent_init(void)
{
unsigned int cpu = smp_processor_id();
struct clock_event_device *cd;

2
arch/mips/kernel/cevt-r4k.c
View File

@ -171,7 +171,7 @@ int c0_compare_int_usable(void)
}
#ifndef CONFIG_MIPS_MT_SMTC
int __cpuinit r4k_clockevent_init(void)
int r4k_clockevent_init(void)
{
unsigned int cpu = smp_processor_id();
struct clock_event_device *cd;

2
arch/mips/kernel/cevt-sb1250.c
View File

@ -107,7 +107,7 @@ static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
void __cpuinit sb1250_clockevent_init(void)
void sb1250_clockevent_init(void)
{
unsigned int cpu = smp_processor_id();
unsigned int irq = K_INT_TIMER_0 + cpu;

Some files were not shown because too many files have changed in this diff Show More