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arm64: dts: rockchip: rename dwmmc node names to mmc

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Current dts files with 'dwmmc' nodes are manually verified.
In order to automate this process rockchip-dw-mshc.txt
has to be converted to yaml. In the new setup
rockchip-dw-mshc.yaml will inherit properties from
mmc-controller.yaml and synopsys-dw-mshc-common.yaml.
'dwmmc' will no longer be a valid name for a node,
so change them all to 'mmc'

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200115185244.18149-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Johan Jonker 2020-01-15 19:52:44 +01:00 committed by Heiko Stuebner
parent 110f027193
commit 3ef7c2558f
5 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/boot/dts/rockchip/px30.dtsi
View File

@ -924,7 +924,7 @@
status = "disabled"; status = "disabled";
}; };
sdmmc: dwmmc@ff370000 { sdmmc: mmc@ff370000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff370000 0x0 0x4000>; reg = <0x0 0xff370000 0x0 0x4000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@ -939,7 +939,7 @@
status = "disabled"; status = "disabled";
}; };
sdio: dwmmc@ff380000 { sdio: mmc@ff380000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff380000 0x0 0x4000>; reg = <0x0 0xff380000 0x0 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@ -954,7 +954,7 @@
status = "disabled"; status = "disabled";
}; };
emmc: dwmmc@ff390000 { emmc: mmc@ff390000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff390000 0x0 0x4000>; reg = <0x0 0xff390000 0x0 0x4000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;

6
arch/arm64/boot/dts/rockchip/rk3308.dtsi
View File

@ -584,7 +584,7 @@
status = "disabled"; status = "disabled";
}; };
sdmmc: dwmmc@ff480000 { sdmmc: mmc@ff480000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff480000 0x0 0x4000>; reg = <0x0 0xff480000 0x0 0x4000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@ -599,7 +599,7 @@
status = "disabled"; status = "disabled";
}; };
emmc: dwmmc@ff490000 { emmc: mmc@ff490000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff490000 0x0 0x4000>; reg = <0x0 0xff490000 0x0 0x4000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
@ -612,7 +612,7 @@
status = "disabled"; status = "disabled";
}; };
sdio: dwmmc@ff4a0000 { sdio: mmc@ff4a0000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff4a0000 0x0 0x4000>; reg = <0x0 0xff4a0000 0x0 0x4000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;

6
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -854,7 +854,7 @@
}; };
}; };
sdmmc: dwmmc@ff500000 { sdmmc: mmc@ff500000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff500000 0x0 0x4000>; reg = <0x0 0xff500000 0x0 0x4000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
@ -866,7 +866,7 @@
status = "disabled"; status = "disabled";
}; };
sdio: dwmmc@ff510000 { sdio: mmc@ff510000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff510000 0x0 0x4000>; reg = <0x0 0xff510000 0x0 0x4000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
@ -878,7 +878,7 @@
status = "disabled"; status = "disabled";
}; };
emmc: dwmmc@ff520000 { emmc: mmc@ff520000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff520000 0x0 0x4000>; reg = <0x0 0xff520000 0x0 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

6
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View File

@ -204,7 +204,7 @@
#clock-cells = <0>; #clock-cells = <0>;
}; };
sdmmc: dwmmc@ff0c0000 { sdmmc: mmc@ff0c0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0c0000 0x0 0x4000>; reg = <0x0 0xff0c0000 0x0 0x4000>;
max-frequency = <150000000>; max-frequency = <150000000>;
@ -218,7 +218,7 @@
status = "disabled"; status = "disabled";
}; };
sdio0: dwmmc@ff0d0000 { sdio0: mmc@ff0d0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0d0000 0x0 0x4000>; reg = <0x0 0xff0d0000 0x0 0x4000>;
max-frequency = <150000000>; max-frequency = <150000000>;
@ -232,7 +232,7 @@
status = "disabled"; status = "disabled";
}; };
emmc: dwmmc@ff0f0000 { emmc: mmc@ff0f0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0f0000 0x0 0x4000>; reg = <0x0 0xff0f0000 0x0 0x4000>;
max-frequency = <150000000>; max-frequency = <150000000>;

4
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -291,7 +291,7 @@
status = "disabled"; status = "disabled";
}; };
sdio0: dwmmc@fe310000 { sdio0: mmc@fe310000 {
compatible = "rockchip,rk3399-dw-mshc", compatible = "rockchip,rk3399-dw-mshc",
"rockchip,rk3288-dw-mshc"; "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe310000 0x0 0x4000>; reg = <0x0 0xfe310000 0x0 0x4000>;
@ -307,7 +307,7 @@
status = "disabled"; status = "disabled";
}; };
sdmmc: dwmmc@fe320000 { sdmmc: mmc@fe320000 {
compatible = "rockchip,rk3399-dw-mshc", compatible = "rockchip,rk3399-dw-mshc",
"rockchip,rk3288-dw-mshc"; "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe320000 0x0 0x4000>; reg = <0x0 0xfe320000 0x0 0x4000>;