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clk: vc5: Use clamp() to restrict PLL range

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The VCO frequency needs to be within a certain range and the driver
enforces this.

Make use of the clamp macro to implement this instead of open-coding it.
This makes the code a bit shorter and also semanticly stronger.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20230114233500.3294789-1-lars@metafoo.de
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Lars-Peter Clausen 2023-01-14 15:34:58 -08:00 committed by Stephen Boyd
parent 1b929c02af
commit 3ed741db04
1 changed files with 1 additions and 4 deletions
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5
drivers/clk/clk-versaclock5.c
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@ -449,10 +449,7 @@ static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
u32 div_int;
u64 div_frc;
if (rate < VC5_PLL_VCO_MIN)
rate = VC5_PLL_VCO_MIN;
if (rate > VC5_PLL_VCO_MAX)
rate = VC5_PLL_VCO_MAX;
rate = clamp(rate, VC5_PLL_VCO_MIN, VC5_PLL_VCO_MAX);
/* Determine integer part, which is 12 bit wide */
div_int = rate / *parent_rate;