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drm/radeon: add fault decode function for CIK
Helpful for debugging GPUVM errors as we can see what hw block and page generated the fault in the log. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -4441,6 +4441,29 @@ void cik_vm_fini(struct radeon_device *rdev)
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{
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}
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/**
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* cik_vm_decode_fault - print human readable fault info
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*
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* @rdev: radeon_device pointer
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* @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
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* @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
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*
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* Print human readable fault information (CIK).
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*/
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static void cik_vm_decode_fault(struct radeon_device *rdev,
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u32 status, u32 addr, u32 mc_client)
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{
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u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
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u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
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u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
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char *block = (char *)&mc_client;
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printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
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protections, vmid, addr,
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(status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
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block, mc_id);
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}
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/**
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* cik_vm_flush - cik vm flush using the CP
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*
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@ -5496,6 +5519,7 @@ int cik_irq_process(struct radeon_device *rdev)
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u32 ring_index;
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bool queue_hotplug = false;
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bool queue_reset = false;
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u32 addr, status, mc_client;
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if (!rdev->ih.enabled || rdev->shutdown)
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return IRQ_NONE;
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@ -5731,11 +5755,15 @@ restart_ih:
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break;
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case 146:
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case 147:
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addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
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status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
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mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
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dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
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dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
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RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
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addr);
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dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
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RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
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status);
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cik_vm_decode_fault(rdev, status, addr, mc_client);
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/* reset addr and status */
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WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
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break;
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@ -136,6 +136,22 @@
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#define VM_INVALIDATE_RESPONSE 0x147c
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#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
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#define PROTECTIONS_MASK (0xf << 0)
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#define PROTECTIONS_SHIFT 0
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/* bit 0: range
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* bit 1: pde0
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* bit 2: valid
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* bit 3: read
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* bit 4: write
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*/
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#define MEMORY_CLIENT_ID_MASK (0xff << 12)
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#define MEMORY_CLIENT_ID_SHIFT 12
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#define MEMORY_CLIENT_RW_MASK (1 << 24)
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#define MEMORY_CLIENT_RW_SHIFT 24
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#define FAULT_VMID_MASK (0xf << 25)
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#define FAULT_VMID_SHIFT 25
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#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4
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#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
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