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riscv, bpf: Support signed div/mod insns
Add support signed div/mod instructions for RV64. Signed-off-by: Pu Lehui <pulehui@huawei.com> Acked-by: Björn Töpel <bjorn@kernel.org> Link: https://lore.kernel.org/r/20230824095001.3408573-6-pulehui@huaweicloud.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
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@ -431,11 +431,21 @@ static inline u32 rv_mulhu(u8 rd, u8 rs1, u8 rs2)
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return rv_r_insn(1, rs2, rs1, 3, rd, 0x33);
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}
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static inline u32 rv_div(u8 rd, u8 rs1, u8 rs2)
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{
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return rv_r_insn(1, rs2, rs1, 4, rd, 0x33);
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}
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static inline u32 rv_divu(u8 rd, u8 rs1, u8 rs2)
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{
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return rv_r_insn(1, rs2, rs1, 5, rd, 0x33);
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}
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static inline u32 rv_rem(u8 rd, u8 rs1, u8 rs2)
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{
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return rv_r_insn(1, rs2, rs1, 6, rd, 0x33);
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}
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static inline u32 rv_remu(u8 rd, u8 rs1, u8 rs2)
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{
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return rv_r_insn(1, rs2, rs1, 7, rd, 0x33);
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@ -776,11 +786,21 @@ static inline u32 rv_mulw(u8 rd, u8 rs1, u8 rs2)
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return rv_r_insn(1, rs2, rs1, 0, rd, 0x3b);
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}
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static inline u32 rv_divw(u8 rd, u8 rs1, u8 rs2)
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{
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return rv_r_insn(1, rs2, rs1, 4, rd, 0x3b);
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}
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static inline u32 rv_divuw(u8 rd, u8 rs1, u8 rs2)
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{
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return rv_r_insn(1, rs2, rs1, 5, rd, 0x3b);
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}
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static inline u32 rv_remw(u8 rd, u8 rs1, u8 rs2)
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{
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return rv_r_insn(1, rs2, rs1, 6, rd, 0x3b);
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}
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static inline u32 rv_remuw(u8 rd, u8 rs1, u8 rs2)
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{
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return rv_r_insn(1, rs2, rs1, 7, rd, 0x3b);
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@ -1107,13 +1107,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
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break;
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case BPF_ALU | BPF_DIV | BPF_X:
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case BPF_ALU64 | BPF_DIV | BPF_X:
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emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx);
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if (off)
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emit(is64 ? rv_div(rd, rd, rs) : rv_divw(rd, rd, rs), ctx);
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else
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emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx);
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if (!is64 && !aux->verifier_zext)
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emit_zext_32(rd, ctx);
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break;
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case BPF_ALU | BPF_MOD | BPF_X:
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case BPF_ALU64 | BPF_MOD | BPF_X:
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emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx);
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if (off)
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emit(is64 ? rv_rem(rd, rd, rs) : rv_remw(rd, rd, rs), ctx);
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else
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emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx);
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if (!is64 && !aux->verifier_zext)
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emit_zext_32(rd, ctx);
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break;
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@ -1284,16 +1290,24 @@ out_be:
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case BPF_ALU | BPF_DIV | BPF_K:
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case BPF_ALU64 | BPF_DIV | BPF_K:
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emit_imm(RV_REG_T1, imm, ctx);
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emit(is64 ? rv_divu(rd, rd, RV_REG_T1) :
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rv_divuw(rd, rd, RV_REG_T1), ctx);
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if (off)
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emit(is64 ? rv_div(rd, rd, RV_REG_T1) :
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rv_divw(rd, rd, RV_REG_T1), ctx);
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else
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emit(is64 ? rv_divu(rd, rd, RV_REG_T1) :
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rv_divuw(rd, rd, RV_REG_T1), ctx);
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if (!is64 && !aux->verifier_zext)
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emit_zext_32(rd, ctx);
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break;
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case BPF_ALU | BPF_MOD | BPF_K:
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case BPF_ALU64 | BPF_MOD | BPF_K:
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emit_imm(RV_REG_T1, imm, ctx);
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emit(is64 ? rv_remu(rd, rd, RV_REG_T1) :
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rv_remuw(rd, rd, RV_REG_T1), ctx);
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if (off)
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emit(is64 ? rv_rem(rd, rd, RV_REG_T1) :
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rv_remw(rd, rd, RV_REG_T1), ctx);
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else
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emit(is64 ? rv_remu(rd, rd, RV_REG_T1) :
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rv_remuw(rd, rd, RV_REG_T1), ctx);
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if (!is64 && !aux->verifier_zext)
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emit_zext_32(rd, ctx);
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break;
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