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drm/amd/display: Disable OTG for mode timing switch on DCN35
[why] Doing a mode timing change causes a hang when OTG is not disabled. [how] Add link_enc null check in disable_otg_wa to cover this case. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -124,7 +124,8 @@ static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *
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if (pipe->top_pipe || pipe->prev_odm_pipe)
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if (pipe->top_pipe || pipe->prev_odm_pipe)
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continue;
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continue;
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if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
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if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||
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!pipe->stream->link_enc)) {
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struct stream_encoder *stream_enc = pipe->stream_res.stream_enc;
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struct stream_encoder *stream_enc = pipe->stream_res.stream_enc;
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if (disable) {
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if (disable) {
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