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drm/i915/gt: Reapply ppgtt enabling after engine resets
The GFX_MODE is reset along with the engine, turning off ppGTT. We need to re-enable it upon resume afterwards. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210114101451.24762-1-chris@chris-wilson.co.uk
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@ -27,8 +27,6 @@ void gen7_ppgtt_enable(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct intel_uncore *uncore = gt->uncore;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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u32 ecochk;
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intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
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@ -41,13 +39,6 @@ void gen7_ppgtt_enable(struct intel_gt *gt)
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ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
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}
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intel_uncore_write(uncore, GAM_ECOCHK, ecochk);
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for_each_engine(engine, gt, id) {
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/* GFX_MODE is per-ring on gen7+ */
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ENGINE_WRITE(engine,
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RING_MODE_GEN7,
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_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
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}
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}
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void gen6_ppgtt_enable(struct intel_gt *gt)
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@ -189,9 +189,16 @@ static void set_pp_dir(struct intel_engine_cs *engine)
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{
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struct i915_address_space *vm = vm_alias(engine->gt->vm);
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if (vm) {
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ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
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ENGINE_WRITE(engine, RING_PP_DIR_BASE, pp_dir(vm));
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if (!vm)
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return;
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ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
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ENGINE_WRITE(engine, RING_PP_DIR_BASE, pp_dir(vm));
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if (INTEL_GEN(engine->i915) >= 7) {
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ENGINE_WRITE(engine,
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RING_MODE_GEN7,
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_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
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}
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}
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