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drm/i915/display/dp: Attach and set drm connector VRR property

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This function sets the VRR property for connector based
on the platform support, EDID monitor range and DP sink
DPCD capability of outputing video without msa
timing information.

v8:
* Use HAS_VRR, remove drm_conn declaration (Jani N)
* Fix typos in Comment (Jani N)
v7:
* Move the helper to separate file (Manasi)
v6:
* Remove unset of prop
v5:
* Fix the vrr prop not being set in kernel (Manasi)
* Unset the prop on connector disconnect (Manasi)
v4:
* Rebase (Mansi)
v3:
* intel_dp_is_vrr_capable can be used for debugfs, make it
non static (Manasi)
v2:
* Just set this in intel_dp_get_modes instead of new hook (Jani)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-2-manasi.d.navare@intel.com
This commit is contained in:
Aditya Swarup 2021-01-22 15:26:31 -08:00 committed by Manasi Navare
parent 5b0c594543
commit 3dafe8a853
2 changed files with 10 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -63,6 +63,7 @@
#include "intel_sideband.h" #include "intel_sideband.h"
#include "intel_tc.h" #include "intel_tc.h"
#include "intel_vdsc.h" #include "intel_vdsc.h"
#include "intel_vrr.h"
#define DP_DPRX_ESI_LEN 14 #define DP_DPRX_ESI_LEN 14
@ -5547,6 +5548,10 @@ static int intel_dp_get_modes(struct drm_connector *connector)
edid = intel_connector->detect_edid; edid = intel_connector->detect_edid;
if (edid) { if (edid) {
int ret = intel_connector_update_modes(connector, edid); int ret = intel_connector_update_modes(connector, edid);
if (intel_vrr_is_capable(connector))
drm_connector_set_vrr_capable_property(connector,
true);
if (ret) if (ret)
return ret; return ret;
} }
@ -5959,6 +5964,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
} }
if (HAS_VRR(dev_priv))
drm_connector_attach_vrr_capable_property(connector);
} }
/** /**

4
drivers/gpu/drm/i915/display/intel_vrr.c
View File

@ -20,10 +20,10 @@ bool intel_vrr_is_capable(struct drm_connector *connector)
intel_dp = intel_attached_dp(to_intel_connector(connector)); intel_dp = intel_attached_dp(to_intel_connector(connector));
/* /*
* DP Sink is capable of Variable refresh video timings if * DP Sink is capable of VRR video timings if
* Ignore MSA bit is set in DPCD. * Ignore MSA bit is set in DPCD.
* EDID monitor range also should be atleast 10 for reasonable * EDID monitor range also should be atleast 10 for reasonable
* Adaptive sync/ VRR end user experience. * Adaptive Sync or Variable Refresh Rate end user experience.
*/ */
return HAS_VRR(i915) && return HAS_VRR(i915) &&
drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) && drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&