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ARM: gic-v3: Work around definition of gic_write_bpr1

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A new accessor for gic_write_bpr1 is added to arch_gicv3.h in 4.9,
whilst the CP15 accessors are redifined in a separate branch.
This leads to a horrible clash, where the new accessor ends up with
a crap "asm volatile" definition.

Work around this by carrying our own definition of gic_write_bpr1,
creating a small conflict which will be obvious to resolve.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Marc Zyngier 2016-09-23 14:23:43 +01:00
parent 6134993789
commit 3d9cd95f90
1 changed files with 9 additions and 0 deletions
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9
arch/arm/include/asm/arch_gicv3.h
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@ -216,6 +216,15 @@ static inline void gic_write_sre(u32 val)
isb();
}
static inline void gic_write_bpr1(u32 val)
{
#if defined(__write_sysreg) && defined(ICC_BPR1)
write_sysreg(val, ICC_BPR1);
#else
asm volatile("mcr " __stringify(ICC_BPR1) : : "r" (val));
#endif
}
/*
* Even in 32bit systems that use LPAE, there is no guarantee that the I/O
* interface provides true 64bit atomic accesses, so using strd/ldrd doesn't