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[IA64-SGI] - New SN hardware support - addr_macros
Update the SN address macros so that they work on both shub1 and shub2. Most of the code to support shub2 was added last year but this patch fixes a few bugs and adds macros to help generate both processor-specific physical addresses & numalink physical addresses. More cleanup & optimization will be done later. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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@ -126,6 +126,7 @@
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#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
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#define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a))
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#define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
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#define IS_TIO_NASID(n) ((n) & 1)
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/* non-II mmr's start at top of big window space (4G) */
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@ -155,10 +156,28 @@
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* the chiplet id is zero. If we implement TIO-TIO dma, we might need
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* to insert a chiplet id into this macro. However, it is our belief
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* right now that this chiplet id will be ICE, which is also zero.
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* Nasid starts on bit 40.
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*/
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#define PHYS_TO_TIODMA(x) ( (((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
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#define PHYS_TO_DMA(x) ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
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#define SH1_TIO_PHYS_TO_DMA(x) \
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((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
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#define SH2_NETWORK_BANK_OFFSET(x) \
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((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
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#define SH2_NETWORK_BANK_SELECT(x) \
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((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4))) \
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>> (sn_hub_info->nasid_shift - 4)) << 36)
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#define SH2_NETWORK_ADDRESS(x) \
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(SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
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#define SH2_TIO_PHYS_TO_DMA(x) \
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(((u64)(NASID_GET(x)) << 40) | SH2_NETWORK_ADDRESS(x))
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#define PHYS_TO_TIODMA(x) \
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(is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
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#define PHYS_TO_DMA(x) \
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((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
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/*
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@ -187,6 +206,7 @@
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#define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
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#define BWIN_WIDGET_MASK 0x7
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#define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
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#define SH1_IS_BIG_WINDOW_ADDR(x) ((x) & BWIN_TOP)
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#define TIO_BWIN_WINDOW_SELECT_MASK 0x7
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#define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
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@ -217,10 +237,6 @@
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#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
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#define TIO_IOSPACE_ADDR(n,x) \
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/* Move in the Chiplet ID for TIO Local Block MMR */ \
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(REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2))
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/*
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* The following macros produce the correct base virtual address for
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* the hub registers. The REMOTE_HUB_* macro produce
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@ -235,18 +251,40 @@
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* Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
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* They're always safe.
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*/
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/* Shub1 TIO & MMR addressing macros */
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#define SH1_TIO_IOSPACE_ADDR(n,x) \
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GLOBAL_MMR_ADDR(n,x)
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#define SH1_REMOTE_BWIN_MMR(n,x) \
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GLOBAL_MMR_ADDR(n,x)
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#define SH1_REMOTE_SWIN_MMR(n,x) \
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(NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
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#define SH1_REMOTE_MMR(n,x) \
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(SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) : \
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SH1_REMOTE_SWIN_MMR(n,x))
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/* Shub1 TIO & MMR addressing macros */
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#define SH2_TIO_IOSPACE_ADDR(n,x) \
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((UNCACHED | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
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#define SH2_REMOTE_MMR(n,x) \
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GLOBAL_MMR_ADDR(n,x)
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/* TIO & MMR addressing macros that work on both shub1 & shub2 */
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#define TIO_IOSPACE_ADDR(n,x) \
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((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) : \
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SH2_TIO_IOSPACE_ADDR(n,x)))
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#define SH_REMOTE_MMR(n,x) \
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(is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
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#define REMOTE_HUB_ADDR(n,x) \
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((n & 1) ? \
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/* TIO: */ \
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(is_shub2() ? \
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/* TIO on Shub2 */ \
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(volatile u64 *)(TIO_IOSPACE_ADDR(n,x)) \
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: /* TIO on shub1 */ \
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(volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
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\
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: /* SHUB1 and SHUB2 MMRs: */ \
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(((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
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: ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x)))))
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(IS_TIO_NASID(n) ? ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) : \
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((volatile u64*)SH_REMOTE_MMR(n,x)))
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#define HUB_L(x) (*((volatile typeof(*x) *)x))
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#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
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