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net/mlx4_en: Avoid a cache line miss in TX completion for single frag skb's
Add frag0_dma/frag0_byte_count into mlx4_en_tx_info to avoid a cache line miss in TX completion for frames having one dma element. (We avoid reading back the tx descriptor) Note this could be extended to 2/3 dma elements later, as we have free room in mlx4_en_tx_info Also, mlx4_en_free_tx_desc() no longer accesses skb_shinfo(). We use a new nr_maps fields in mlx4_en_tx_info to avoid 2 or 3 cache misses. Signed-off-by: Eric Dumazet <edumazet@google.com> Signed-off-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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dc9b06d156
commit
3d03641cb4
@ -259,38 +259,40 @@ static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring,
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int index, u8 owner, u64 timestamp)
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
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struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
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struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
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struct sk_buff *skb = tx_info->skb;
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struct skb_frag_struct *frag;
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void *end = ring->buf + ring->buf_size;
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int frags = skb_shinfo(skb)->nr_frags;
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struct sk_buff *skb = tx_info->skb;
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int nr_maps = tx_info->nr_maps;
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int i;
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struct skb_shared_hwtstamps hwts;
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if (timestamp) {
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mlx4_en_fill_hwtstamps(mdev, &hwts, timestamp);
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if (unlikely(timestamp)) {
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struct skb_shared_hwtstamps hwts;
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mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
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skb_tstamp_tx(skb, &hwts);
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}
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/* Optimize the common case when there are no wraparounds */
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if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
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if (!tx_info->inl) {
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if (tx_info->linear) {
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if (tx_info->linear)
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dma_unmap_single(priv->ddev,
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(dma_addr_t) be64_to_cpu(data->addr),
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be32_to_cpu(data->byte_count),
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PCI_DMA_TODEVICE);
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++data;
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}
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for (i = 0; i < frags; i++) {
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frag = &skb_shinfo(skb)->frags[i];
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tx_info->map0_dma,
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tx_info->map0_byte_count,
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PCI_DMA_TODEVICE);
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else
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dma_unmap_page(priv->ddev,
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(dma_addr_t) be64_to_cpu(data[i].addr),
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skb_frag_size(frag), PCI_DMA_TODEVICE);
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tx_info->map0_dma,
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tx_info->map0_byte_count,
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PCI_DMA_TODEVICE);
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for (i = 1; i < nr_maps; i++) {
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data++;
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dma_unmap_page(priv->ddev,
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(dma_addr_t)be64_to_cpu(data->addr),
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be32_to_cpu(data->byte_count),
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PCI_DMA_TODEVICE);
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}
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}
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} else {
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@ -299,23 +301,25 @@ static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
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data = ring->buf + ((void *)data - end);
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}
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if (tx_info->linear) {
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if (tx_info->linear)
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dma_unmap_single(priv->ddev,
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(dma_addr_t) be64_to_cpu(data->addr),
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be32_to_cpu(data->byte_count),
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PCI_DMA_TODEVICE);
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++data;
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}
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for (i = 0; i < frags; i++) {
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tx_info->map0_dma,
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tx_info->map0_byte_count,
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PCI_DMA_TODEVICE);
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else
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dma_unmap_page(priv->ddev,
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tx_info->map0_dma,
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tx_info->map0_byte_count,
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PCI_DMA_TODEVICE);
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for (i = 1; i < nr_maps; i++) {
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data++;
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/* Check for wraparound before unmapping */
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if ((void *) data >= end)
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data = ring->buf;
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frag = &skb_shinfo(skb)->frags[i];
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dma_unmap_page(priv->ddev,
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(dma_addr_t) be64_to_cpu(data->addr),
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skb_frag_size(frag), PCI_DMA_TODEVICE);
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++data;
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(dma_addr_t)be64_to_cpu(data->addr),
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be32_to_cpu(data->byte_count),
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PCI_DMA_TODEVICE);
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}
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}
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}
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@ -751,19 +755,22 @@ netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
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tx_info->linear = (lso_header_size < skb_headlen(skb) &&
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!is_inline(ring->inline_thold, skb, NULL)) ? 1 : 0;
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data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1;
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tx_info->nr_maps = skb_shinfo(skb)->nr_frags + tx_info->linear;
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data += tx_info->nr_maps - 1;
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if (is_inline(ring->inline_thold, skb, &fragptr)) {
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tx_info->inl = 1;
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} else {
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dma_addr_t dma = 0;
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u32 byte_count = 0;
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/* Map fragments if any */
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for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) {
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const struct skb_frag_struct *frag;
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dma_addr_t dma;
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frag = &skb_shinfo(skb)->frags[i];
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byte_count = skb_frag_size(frag);
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dma = skb_frag_dma_map(ddev, frag,
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0, skb_frag_size(frag),
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0, byte_count,
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DMA_TO_DEVICE);
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if (dma_mapping_error(ddev, dma))
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goto tx_drop_unmap;
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@ -771,14 +778,13 @@ netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
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data->addr = cpu_to_be64(dma);
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data->lkey = ring->mr_key;
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wmb();
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data->byte_count = cpu_to_be32(skb_frag_size(frag));
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data->byte_count = cpu_to_be32(byte_count);
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--data;
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}
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/* Map linear part if needed */
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if (tx_info->linear) {
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u32 byte_count = skb_headlen(skb) - lso_header_size;
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dma_addr_t dma;
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byte_count = skb_headlen(skb) - lso_header_size;
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dma = dma_map_single(ddev, skb->data +
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lso_header_size, byte_count,
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@ -792,6 +798,9 @@ netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
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data->byte_count = cpu_to_be32(byte_count);
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}
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tx_info->inl = 0;
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/* tx completion can avoid cache line miss for common cases */
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tx_info->map0_dma = dma;
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tx_info->map0_byte_count = byte_count;
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}
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/*
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@ -216,12 +216,15 @@ enum cq_type {
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struct mlx4_en_tx_info {
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struct sk_buff *skb;
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dma_addr_t map0_dma;
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u32 map0_byte_count;
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u32 nr_txbb;
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u32 nr_bytes;
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u8 linear;
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u8 data_offset;
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u8 inl;
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u8 ts_requested;
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u8 nr_maps;
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} ____cacheline_aligned_in_smp;
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