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drm/radeon: Allow setting shader registers using DMA/COPY packet3 on SI.

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Mesa uses a COPY_DATA packet to copy the grid size for indirect dispatches
into COMPUTE_USER_DATA_*.

Setting those registers with a SET_SH_REG packet is allowed, not allowing
them with other packets seems like an oversight.

v2: Clarify commit message.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Bas Nieuwenhuizen 2016-04-15 02:47:49 +02:00 committed by Alex Deucher
parent b76af4a419
commit 3d02b7fee9
2 changed files with 6 additions and 1 deletions
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3
drivers/gpu/drm/radeon/radeon_drv.c
View File

@ -94,9 +94,10 @@
* 2.42.0 - Add VCE/VUI (Video Usability Information) support
* 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
* 2.44.0 - SET_APPEND_CNT packet3 support
* 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
*/
#define KMS_DRIVER_MAJOR 2
#define KMS_DRIVER_MINOR 44
#define KMS_DRIVER_MINOR 45
#define KMS_DRIVER_PATCHLEVEL 0
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
int radeon_driver_unload_kms(struct drm_device *dev);

4
drivers/gpu/drm/radeon/si.c
View File

@ -4364,6 +4364,10 @@ static bool si_vm_reg_valid(u32 reg)
if (reg >= 0x28000)
return true;
/* shader regs are also fine */
if (reg >= 0xB000 && reg < 0xC000)
return true;
/* check config regs */
switch (reg) {
case GRBM_GFX_INDEX: