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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Browse Source 
Pull MIPS update from Ralf Baechle:
 - Fix a build error if <linux/printk.h> is included without
   <linux/linkage.h> having been included before.
 - Cleanup and fix the damage done by the generic idle loop patch.
 - A kprobes fix that brings the MIPS code in line with what other
   architectures are for quite a while already.
 - Wire up the native getdents64(2) syscall for 64 bit - for some reason
   it was only for the compat ABIs.  This has been reported to cause an
   application issue.  This turned out bigger than I meant but the wait
   instruction support code was driving me nuts.

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: N64: Wire getdents64(2)
  kprobes/mips: Fix to check double free of insn slot
  MIPS: Idle: Break r4k_wait into two functions and fix it.
  MIPS: Idle: Do address fiddlery in helper functions.
  MIPS: Idle: Consolidate all declarations in <asm/idle.h>.
  MIPS: Idle: Don't call local_irq_disable() in cpu_wait() implementations.
  MIPS: Idle: Re-enable irqs at the end of r3081, au1k and loongson2 cpu_wait.
  MIPS: Idle: Make call of function pointer readable.
  MIPS: Idle: Consistently reformat inline assembler.
  MIPS: Idle: cleaup SMTC idle hook as per Linux coding style.
  MIPS: Consolidate idle loop / WAIT instruction support in a single file.
  MIPS: clock.h: Remove declaration of cpu_wait.
  Add include dependencies to <linux/printk.h>.
  MIPS: Rewrite pfn_valid to work in modules, too.
This commit is contained in:
Linus Torvalds 2013-05-22 18:05:45 -07:00
commit 3cb7a59fd8
30 changed files with 309 additions and 237 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/mips/alchemy/board-gpr.c
View File

@ -31,6 +31,7 @@
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
#include <asm/bootinfo.h>
#include <asm/idle.h>
#include <asm/reboot.h>
#include <asm/mach-au1x00/au1000.h>
#include <prom.h>

1
arch/mips/alchemy/common/time.c
View File

@ -36,6 +36,7 @@
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <asm/idle.h>
#include <asm/processor.h>
#include <asm/time.h>
#include <asm/mach-au1x00/au1000.h>

1
arch/mips/ath79/setup.c
View File

@ -19,6 +19,7 @@
#include <linux/clk.h>
#include <asm/bootinfo.h>
#include <asm/idle.h>
#include <asm/time.h> /* for mips_hpt_frequency */
#include <asm/reboot.h> /* for _machine_{restart,halt} */
#include <asm/mips_machine.h>

1
arch/mips/cobalt/reset.c
View File

@ -12,6 +12,7 @@
#include <linux/io.h>
#include <linux/leds.h>
#include <asm/idle.h>
#include <asm/processor.h>
#include <cobalt.h>

2
arch/mips/include/asm/clock.h
View File

@ -6,8 +6,6 @@
#include <linux/seq_file.h>
#include <linux/clk.h>
extern void (*cpu_wait) (void);
struct clk;
struct clk_ops {

23
arch/mips/include/asm/idle.h Normal file
View File

@ -0,0 +1,23 @@
#ifndef __ASM_IDLE_H
#define __ASM_IDLE_H
#include <linux/linkage.h>
extern void (*cpu_wait)(void);
extern void r4k_wait(void);
extern asmlinkage void __r4k_wait(void);
extern void r4k_wait_irqoff(void);
extern void __pastwait(void);
static inline int using_rollback_handler(void)
{
return cpu_wait == r4k_wait;
}
static inline int address_is_in_r4k_wait_irqoff(unsigned long addr)
{
return addr >= (unsigned long)r4k_wait_irqoff &&
addr < (unsigned long)__pastwait;
}
#endif /* __ASM_IDLE_H */

15
arch/mips/include/asm/page.h
View File

@ -171,14 +171,13 @@ typedef struct { unsigned long pgprot; } pgprot_t;
#ifdef CONFIG_FLATMEM
#define pfn_valid(pfn) \
({ \
unsigned long __pfn = (pfn); \
/* avoid <linux/bootmem.h> include hell */ \
extern unsigned long min_low_pfn; \
\
__pfn >= min_low_pfn && __pfn < max_mapnr; \
})
static inline int pfn_valid(unsigned long pfn)
{
/* avoid <linux/mm.h> include hell */
extern unsigned long max_mapnr;
return pfn >= ARCH_PFN_OFFSET && pfn < max_mapnr;
}
#elif defined(CONFIG_SPARSEMEM)

1
arch/mips/include/asm/processor.h
View File

@ -28,7 +28,6 @@
/*
* System setup and hardware flags..
*/
extern void (*cpu_wait)(void);
extern unsigned int vced_count, vcei_count;

5
arch/mips/include/uapi/asm/unistd.h
View File

@ -694,16 +694,17 @@
#define __NR_process_vm_writev (__NR_Linux + 305)
#define __NR_kcmp (__NR_Linux + 306)
#define __NR_finit_module (__NR_Linux + 307)
#define __NR_getdents64 (__NR_Linux + 308)
/*
* Offset of the last Linux 64-bit flavoured syscall
*/
#define __NR_Linux_syscalls 307
#define __NR_Linux_syscalls 308
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
#define __NR_64_Linux 5000
#define __NR_64_Linux_syscalls 307
#define __NR_64_Linux_syscalls 308
#if _MIPS_SIM == _MIPS_SIM_NABI32

2
arch/mips/kernel/Makefile
View File

@ -4,7 +4,7 @@
extra-y := head.o vmlinux.lds
obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
obj-y += cpu-probe.o branch.o entry.o genex.o idle.o irq.o process.o \
prom.o ptrace.o reset.o setup.o signal.o syscall.o \
time.o topology.o traps.o unaligned.o watch.o vdso.o

198
arch/mips/kernel/cpu-probe.c
View File

@ -27,105 +27,6 @@
#include <asm/spram.h>
#include <asm/uaccess.h>
/*
* Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
* the implementation of the "wait" feature differs between CPU families. This
* points to the function that implements CPU specific wait.
* The wait instruction stops the pipeline and reduces the power consumption of
* the CPU very much.
*/
void (*cpu_wait)(void);
EXPORT_SYMBOL(cpu_wait);
static void r3081_wait(void)
{
unsigned long cfg = read_c0_conf();
write_c0_conf(cfg | R30XX_CONF_HALT);
}
static void r39xx_wait(void)
{
local_irq_disable();
if (!need_resched())
write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
local_irq_enable();
}
extern void r4k_wait(void);
/*
* This variant is preferable as it allows testing need_resched and going to
* sleep depending on the outcome atomically. Unfortunately the "It is
* implementation-dependent whether the pipeline restarts when a non-enabled
* interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
* using this version a gamble.
*/
void r4k_wait_irqoff(void)
{
local_irq_disable();
if (!need_resched())
__asm__(" .set push \n"
" .set mips3 \n"
" wait \n"
" .set pop \n");
local_irq_enable();
__asm__(" .globl __pastwait \n"
"__pastwait: \n");
}
/*
* The RM7000 variant has to handle erratum 38. The workaround is to not
* have any pending stores when the WAIT instruction is executed.
*/
static void rm7k_wait_irqoff(void)
{
local_irq_disable();
if (!need_resched())
__asm__(
" .set push \n"
" .set mips3 \n"
" .set noat \n"
" mfc0 $1, $12 \n"
" sync \n"
" mtc0 $1, $12 # stalls until W stage \n"
" wait \n"
" mtc0 $1, $12 # stalls until W stage \n"
" .set pop \n");
local_irq_enable();
}
/*
* The Au1xxx wait is available only if using 32khz counter or
* external timer source, but specifically not CP0 Counter.
* alchemy/common/time.c may override cpu_wait!
*/
static void au1k_wait(void)
{
__asm__(" .set mips3 \n"
" cache 0x14, 0(%0) \n"
" cache 0x14, 32(%0) \n"
" sync \n"
" nop \n"
" wait \n"
" nop \n"
" nop \n"
" nop \n"
" nop \n"
" .set mips0 \n"
: : "r" (au1k_wait));
}
static int __initdata nowait;
static int __init wait_disable(char *s)
{
nowait = 1;
return 1;
}
__setup("nowait", wait_disable);
static int __cpuinitdata mips_fpu_disabled;
static int __init fpu_disable(char *s)
@ -150,105 +51,6 @@ static int __init dsp_disable(char *s)
__setup("nodsp", dsp_disable);
void __init check_wait(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
if (nowait) {
printk("Wait instruction disabled.\n");
return;
}
switch (c->cputype) {
case CPU_R3081:
case CPU_R3081E:
cpu_wait = r3081_wait;
break;
case CPU_TX3927:
cpu_wait = r39xx_wait;
break;
case CPU_R4200:
/* case CPU_R4300: */
case CPU_R4600:
case CPU_R4640:
case CPU_R4650:
case CPU_R4700:
case CPU_R5000:
case CPU_R5500:
case CPU_NEVADA:
case CPU_4KC:
case CPU_4KEC:
case CPU_4KSC:
case CPU_5KC:
case CPU_25KF:
case CPU_PR4450:
case CPU_BMIPS3300:
case CPU_BMIPS4350:
case CPU_BMIPS4380:
case CPU_BMIPS5000:
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
case CPU_JZRISC:
case CPU_LOONGSON1:
case CPU_XLR:
case CPU_XLP:
cpu_wait = r4k_wait;
break;
case CPU_RM7000:
cpu_wait = rm7k_wait_irqoff;
break;
case CPU_M14KC:
case CPU_M14KEC:
case CPU_24K:
case CPU_34K:
case CPU_1004K:
cpu_wait = r4k_wait;
if (read_c0_config7() & MIPS_CONF7_WII)
cpu_wait = r4k_wait_irqoff;
break;
case CPU_74K:
cpu_wait = r4k_wait;
if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
cpu_wait = r4k_wait_irqoff;
break;
case CPU_TX49XX:
cpu_wait = r4k_wait_irqoff;
break;
case CPU_ALCHEMY:
cpu_wait = au1k_wait;
break;
case CPU_20KC:
/*
* WAIT on Rev1.0 has E1, E2, E3 and E16.
* WAIT on Rev2.0 and Rev3.0 has E16.
* Rev3.1 WAIT is nop, why bother
*/
if ((c->processor_id & 0xff) <= 0x64)
break;
/*
* Another rev is incremeting c0_count at a reduced clock
* rate while in WAIT mode. So we basically have the choice
* between using the cp0 timer as clocksource or avoiding
* the WAIT instruction. Until more details are known,
* disable the use of WAIT for 20Kc entirely.
cpu_wait = r4k_wait;
*/
break;
case CPU_RM9000:
if ((c->processor_id & 0x00ff) >= 0x40)
cpu_wait = r4k_wait;
break;
default:
break;
}
}
static inline void check_errata(void)
{
struct cpuinfo_mips *c = &current_cpu_data;

6
arch/mips/kernel/genex.S
View File

@ -122,7 +122,7 @@ handle_vcei:
__FINIT
.align 5 /* 32 byte rollback region */
LEAF(r4k_wait)
LEAF(__r4k_wait)
.set push
.set noreorder
/* start of rollback region */
@ -146,14 +146,14 @@ LEAF(r4k_wait)
jr ra
nop
.set pop
END(r4k_wait)
END(__r4k_wait)
.macro BUILD_ROLLBACK_PROLOGUE handler
FEXPORT(rollback_\handler)
.set push
.set noat
MFC0 k0, CP0_EPC
PTR_LA k1, r4k_wait
PTR_LA k1, __r4k_wait
ori k0, 0x1f /* 32 byte rollback region */
xori k0, 0x1f
bne k0, k1, 9f

244
arch/mips/kernel/idle.c Normal file
View File

@ -0,0 +1,244 @@
/*
* MIPS idle loop and WAIT instruction support.
*
* Copyright (C) xxxx the Anonymous
* Copyright (C) 1994 - 2006 Ralf Baechle
* Copyright (C) 2003, 2004 Maciej W. Rozycki
* Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/export.h>
#include <linux/init.h>
#include <linux/irqflags.h>
#include <linux/printk.h>
#include <linux/sched.h>
#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <asm/idle.h>
#include <asm/mipsregs.h>
/*
* Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
* the implementation of the "wait" feature differs between CPU families. This
* points to the function that implements CPU specific wait.
* The wait instruction stops the pipeline and reduces the power consumption of
* the CPU very much.
*/
void (*cpu_wait)(void);
EXPORT_SYMBOL(cpu_wait);
static void r3081_wait(void)
{
unsigned long cfg = read_c0_conf();
write_c0_conf(cfg | R30XX_CONF_HALT);
local_irq_enable();
}
static void r39xx_wait(void)
{
if (!need_resched())
write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
local_irq_enable();
}
void r4k_wait(void)
{
local_irq_enable();
__r4k_wait();
}
/*
* This variant is preferable as it allows testing need_resched and going to
* sleep depending on the outcome atomically. Unfortunately the "It is
* implementation-dependent whether the pipeline restarts when a non-enabled
* interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
* using this version a gamble.
*/
void r4k_wait_irqoff(void)
{
if (!need_resched())
__asm__(
" .set push \n"
" .set mips3 \n"
" wait \n"
" .set pop \n");
local_irq_enable();
__asm__(
" .globl __pastwait \n"
"__pastwait: \n");
}
/*
* The RM7000 variant has to handle erratum 38. The workaround is to not
* have any pending stores when the WAIT instruction is executed.
*/
static void rm7k_wait_irqoff(void)
{
if (!need_resched())
__asm__(
" .set push \n"
" .set mips3 \n"
" .set noat \n"
" mfc0 $1, $12 \n"
" sync \n"
" mtc0 $1, $12 # stalls until W stage \n"
" wait \n"
" mtc0 $1, $12 # stalls until W stage \n"
" .set pop \n");
local_irq_enable();
}
/*
* The Au1xxx wait is available only if using 32khz counter or
* external timer source, but specifically not CP0 Counter.
* alchemy/common/time.c may override cpu_wait!
*/
static void au1k_wait(void)
{
__asm__(
" .set mips3 \n"
" cache 0x14, 0(%0) \n"
" cache 0x14, 32(%0) \n"
" sync \n"
" nop \n"
" wait \n"
" nop \n"
" nop \n"
" nop \n"
" nop \n"
" .set mips0 \n"
: : "r" (au1k_wait));
local_irq_enable();
}
static int __initdata nowait;
static int __init wait_disable(char *s)
{
nowait = 1;
return 1;
}
__setup("nowait", wait_disable);
void __init check_wait(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
if (nowait) {
printk("Wait instruction disabled.\n");
return;
}
switch (c->cputype) {
case CPU_R3081:
case CPU_R3081E:
cpu_wait = r3081_wait;
break;
case CPU_TX3927:
cpu_wait = r39xx_wait;
break;
case CPU_R4200:
/* case CPU_R4300: */
case CPU_R4600:
case CPU_R4640:
case CPU_R4650:
case CPU_R4700:
case CPU_R5000:
case CPU_R5500:
case CPU_NEVADA:
case CPU_4KC:
case CPU_4KEC:
case CPU_4KSC:
case CPU_5KC:
case CPU_25KF:
case CPU_PR4450:
case CPU_BMIPS3300:
case CPU_BMIPS4350:
case CPU_BMIPS4380:
case CPU_BMIPS5000:
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
case CPU_JZRISC:
case CPU_LOONGSON1:
case CPU_XLR:
case CPU_XLP:
cpu_wait = r4k_wait;
break;
case CPU_RM7000:
cpu_wait = rm7k_wait_irqoff;
break;
case CPU_M14KC:
case CPU_M14KEC:
case CPU_24K:
case CPU_34K:
case CPU_1004K:
cpu_wait = r4k_wait;
if (read_c0_config7() & MIPS_CONF7_WII)
cpu_wait = r4k_wait_irqoff;
break;
case CPU_74K:
cpu_wait = r4k_wait;
if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
cpu_wait = r4k_wait_irqoff;
break;
case CPU_TX49XX:
cpu_wait = r4k_wait_irqoff;
break;
case CPU_ALCHEMY:
cpu_wait = au1k_wait;
break;
case CPU_20KC:
/*
* WAIT on Rev1.0 has E1, E2, E3 and E16.
* WAIT on Rev2.0 and Rev3.0 has E16.
* Rev3.1 WAIT is nop, why bother
*/
if ((c->processor_id & 0xff) <= 0x64)
break;
/*
* Another rev is incremeting c0_count at a reduced clock
* rate while in WAIT mode. So we basically have the choice
* between using the cp0 timer as clocksource or avoiding
* the WAIT instruction. Until more details are known,
* disable the use of WAIT for 20Kc entirely.
cpu_wait = r4k_wait;
*/
break;
case CPU_RM9000:
if ((c->processor_id & 0x00ff) >= 0x40)
cpu_wait = r4k_wait;
break;
default:
break;
}
}
static void smtc_idle_hook(void)
{
#ifdef CONFIG_MIPS_MT_SMTC
void smtc_idle_loop_hook(void);
smtc_idle_loop_hook();
#endif
}
void arch_cpu_idle(void)
{
smtc_idle_hook();
if (cpu_wait)
cpu_wait();
else
local_irq_enable();
}

5
arch/mips/kernel/kprobes.c
View File

@ -207,7 +207,10 @@ void __kprobes arch_disarm_kprobe(struct kprobe *p)
void __kprobes arch_remove_kprobe(struct kprobe *p)
{
free_insn_slot(p->ainsn.insn, 0);
if (p->ainsn.insn) {
free_insn_slot(p->ainsn.insn, 0);
p->ainsn.insn = NULL;
}
}
static void save_previous_kprobe(struct kprobe_ctlblk *kcb)

1
arch/mips/kernel/proc.c
View File

@ -10,6 +10,7 @@
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/cpu-features.h>
#include <asm/idle.h>
#include <asm/mipsregs.h>
#include <asm/processor.h>
#include <asm/prom.h>

13
arch/mips/kernel/process.c
View File

@ -51,19 +51,6 @@ void arch_cpu_idle_dead(void)
}
#endif
void arch_cpu_idle(void)
{
#ifdef CONFIG_MIPS_MT_SMTC
extern void smtc_idle_loop_hook(void);
smtc_idle_loop_hook();
#endif
if (cpu_wait)
(*cpu_wait)();
else
local_irq_enable();
}
asmlinkage void ret_from_fork(void);
asmlinkage void ret_from_kernel_thread(void);

1
arch/mips/kernel/scall64-64.S
View File

@ -423,4 +423,5 @@ sys_call_table:
PTR sys_process_vm_writev /* 5305 */
PTR sys_kcmp
PTR sys_finit_module
PTR sys_getdents64
.size sys_call_table,.-sys_call_table

1
arch/mips/kernel/smp.c
View File

@ -37,6 +37,7 @@
#include <linux/atomic.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/idle.h>
#include <asm/r4k-timer.h>
#include <asm/mmu_context.h>
#include <asm/time.h>

5
arch/mips/kernel/smtc.c
View File

@ -34,6 +34,7 @@
#include <asm/hardirq.h>
#include <asm/hazards.h>
#include <asm/irq.h>
#include <asm/idle.h>
#include <asm/mmu_context.h>
#include <asm/mipsregs.h>
#include <asm/cacheflush.h>
@ -858,7 +859,6 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
unsigned long flags;
int mtflags;
unsigned long tcrestart;
extern void r4k_wait_irqoff(void), __pastwait(void);
int set_resched_flag = (type == LINUX_SMP_IPI &&
action == SMP_RESCHEDULE_YOURSELF);
@ -914,8 +914,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
*/
if (cpu_wait == r4k_wait_irqoff) {
tcrestart = read_tc_c0_tcrestart();
if (tcrestart >= (unsigned long)r4k_wait_irqoff
&& tcrestart < (unsigned long)__pastwait) {
if (address_is_in_r4k_wait_irqoff(tcrestart)) {
write_tc_c0_tcrestart(__pastwait);
tcstatus &= ~TCSTATUS_IXMT;
write_tc_c0_tcstatus(tcstatus);

9
arch/mips/kernel/traps.c
View File

@ -41,6 +41,7 @@
#include <asm/dsp.h>
#include <asm/fpu.h>
#include <asm/fpu_emulator.h>
#include <asm/idle.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/module.h>
@ -57,7 +58,6 @@
#include <asm/uasm.h>
extern void check_wait(void);
extern asmlinkage void r4k_wait(void);
extern asmlinkage void rollback_handle_int(void);
extern asmlinkage void handle_int(void);
extern u32 handle_tlbl[];
@ -1542,7 +1542,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
extern char except_vec_vi, except_vec_vi_lui;
extern char except_vec_vi_ori, except_vec_vi_end;
extern char rollback_except_vec_vi;
char *vec_start = (cpu_wait == r4k_wait) ?
char *vec_start = using_rollback_handler() ?
&rollback_except_vec_vi : &except_vec_vi;
#ifdef CONFIG_MIPS_MT_SMTC
/*
@ -1812,10 +1812,8 @@ void __init trap_init(void)
extern char except_vec4;
extern char except_vec3_r4000;
unsigned long i;
int rollback;
check_wait();
rollback = (cpu_wait == r4k_wait);
#if defined(CONFIG_KGDB)
if (kgdb_early_setup)
@ -1892,7 +1890,8 @@ void __init trap_init(void)
if (board_be_init)
board_be_init();
set_except_vector(0, rollback ? rollback_handle_int : handle_int);
set_except_vector(0, using_rollback_handler() ? rollback_handle_int
: handle_int);
set_except_vector(1, handle_tlbm);
set_except_vector(2, handle_tlbl);
set_except_vector(3, handle_tlbs);

1
arch/mips/loongson/common/reset.c
View File

@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/pm.h>
#include <asm/idle.h>
#include <asm/reboot.h>
#include <loongson.h>

1
arch/mips/loongson1/common/reset.c
View File

@ -9,6 +9,7 @@
#include <linux/io.h>
#include <linux/pm.h>
#include <asm/idle.h>
#include <asm/reboot.h>
#include <loongson1.h>

1
arch/mips/netlogic/xlp/setup.c
View File

@ -37,6 +37,7 @@
#include <linux/pm.h>
#include <linux/bootmem.h>
#include <asm/idle.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <asm/bootinfo.h>

1
arch/mips/netlogic/xlr/setup.c
View File

@ -36,6 +36,7 @@
#include <linux/serial_8250.h>
#include <linux/pm.h>
#include <asm/idle.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <asm/bootinfo.h>

1
arch/mips/pmcs-msp71xx/msp_setup.c
View File

@ -12,6 +12,7 @@
#include <asm/bootinfo.h>
#include <asm/cacheflush.h>
#include <asm/idle.h>
#include <asm/r4kcache.h>
#include <asm/reboot.h>
#include <asm/smp-ops.h>

1
arch/mips/txx9/generic/setup.c
View File

@ -26,6 +26,7 @@
#include <linux/slab.h>
#include <linux/irq.h>
#include <asm/bootinfo.h>
#include <asm/idle.h>
#include <asm/time.h>
#include <asm/reboot.h>
#include <asm/r4kcache.h>

1
arch/mips/vr41xx/common/pmu.c
View File

@ -27,6 +27,7 @@
#include <asm/cacheflush.h>
#include <asm/cpu.h>
#include <asm/idle.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/reboot.h>

1
arch/mips/wrppmc/reset.c
View File

@ -9,6 +9,7 @@
#include <linux/kernel.h>
#include <asm/cacheflush.h>
#include <asm/idle.h>
#include <asm/mipsregs.h>
#include <asm/processor.h>

2
drivers/cpufreq/loongson2_cpufreq.c
View File

@ -18,6 +18,7 @@
#include <linux/platform_device.h>
#include <asm/clock.h>
#include <asm/idle.h>
#include <asm/mach-loongson/loongson.h>
@ -200,6 +201,7 @@ static void loongson2_cpu_wait(void)
LOONGSON_CHIPCFG0 &= ~0x7; /* Put CPU into wait mode */
LOONGSON_CHIPCFG0 = cpu_freq; /* Restore CPU state */
spin_unlock_irqrestore(&loongson2_wait_lock, flags);
local_irq_enable();
}
static int __init cpufreq_init(void)

1
include/linux/printk.h
View File

@ -4,6 +4,7 @@
#include <stdarg.h>
#include <linux/init.h>
#include <linux/kern_levels.h>
#include <linux/linkage.h>
extern const char linux_banner[];
extern const char linux_proc_banner[];