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irq_remapping/vt-d: Clean up unsued code
Now we have converted to hierarchical irqdomains, so clean up unused code. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Tested-by: Joerg Roedel <jroedel@suse.de> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: David Cohen <david.a.cohen@linux.intel.com> Cc: Sander Eikelenboom <linux@eikelenboom.it> Cc: David Vrabel <david.vrabel@citrix.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: iommu@lists.linux-foundation.org Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dimitri Sivanich <sivanich@sgi.com> Cc: Joerg Roedel <joro@8bytes.org> Link: http://lkml.kernel.org/r/1428978610-28986-11-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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9880534989
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3c6e567509
@ -63,35 +63,6 @@ static struct irq_domain_ops intel_ir_domain_ops;
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static int __init parse_ioapics_under_ir(void);
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static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
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{
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struct irq_cfg *cfg = irq_cfg(irq);
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return cfg ? &cfg->irq_2_iommu : NULL;
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}
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static int get_irte(int irq, struct irte *entry)
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{
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struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
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unsigned long flags;
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int index;
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if (!entry || !irq_iommu)
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return -1;
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
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if (unlikely(!irq_iommu->iommu)) {
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return -1;
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}
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
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*entry = *(irq_iommu->iommu->ir_table->base + index);
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return 0;
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}
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static int alloc_irte(struct intel_iommu *iommu, int irq,
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struct irq_2_iommu *irq_iommu, u16 count)
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{
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@ -229,29 +200,6 @@ static int clear_entries(struct irq_2_iommu *irq_iommu)
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return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
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}
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static int free_irte(int irq)
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{
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struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
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unsigned long flags;
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int rc;
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if (!irq_iommu || irq_iommu->iommu == NULL)
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return -1;
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
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rc = clear_entries(irq_iommu);
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irq_iommu->iommu = NULL;
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irq_iommu->irte_index = 0;
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irq_iommu->sub_handle = 0;
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irq_iommu->irte_mask = 0;
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return rc;
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}
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/*
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* source validation type
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*/
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@ -932,8 +880,7 @@ error:
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return -1;
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}
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static void prepare_irte(struct irte *irte, int vector,
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unsigned int dest)
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static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
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{
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memset(irte, 0, sizeof(*irte));
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@ -953,135 +900,6 @@ static void prepare_irte(struct irte *irte, int vector,
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irte->redir_hint = 1;
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}
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static int intel_setup_ioapic_entry(int irq,
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struct IO_APIC_route_entry *route_entry,
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unsigned int destination, int vector,
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struct io_apic_irq_attr *attr)
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{
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int ioapic_id = mpc_ioapic_id(attr->ioapic);
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struct intel_iommu *iommu;
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struct IR_IO_APIC_route_entry *entry;
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struct irte irte;
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int index;
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down_read(&dmar_global_lock);
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iommu = map_ioapic_to_ir(ioapic_id);
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if (!iommu) {
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pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
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index = -ENODEV;
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} else {
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index = alloc_irte(iommu, irq, irq_2_iommu(irq), 1);
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if (index < 0) {
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pr_warn("Failed to allocate IRTE for ioapic %d\n",
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ioapic_id);
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index = -ENOMEM;
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}
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}
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up_read(&dmar_global_lock);
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if (index < 0)
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return index;
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prepare_irte(&irte, vector, destination);
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/* Set source-id of interrupt request */
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set_ioapic_sid(&irte, ioapic_id);
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modify_irte(irq_2_iommu(irq), &irte);
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apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
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"Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
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"Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
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"Avail:%X Vector:%02X Dest:%08X "
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"SID:%04X SQ:%X SVT:%X)\n",
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attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
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irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
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irte.avail, irte.vector, irte.dest_id,
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irte.sid, irte.sq, irte.svt);
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entry = (struct IR_IO_APIC_route_entry *)route_entry;
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memset(entry, 0, sizeof(*entry));
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entry->index2 = (index >> 15) & 0x1;
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entry->zero = 0;
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entry->format = 1;
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entry->index = (index & 0x7fff);
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/*
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* IO-APIC RTE will be configured with virtual vector.
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* irq handler will do the explicit EOI to the io-apic.
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*/
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entry->vector = attr->ioapic_pin;
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entry->mask = 0; /* enable IRQ */
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entry->trigger = attr->trigger;
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entry->polarity = attr->polarity;
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/* Mask level triggered irqs.
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* Use IRQ_DELAYED_DISABLE for edge triggered irqs.
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*/
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if (attr->trigger)
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entry->mask = 1;
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return 0;
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}
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/*
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* Migrate the IO-APIC irq in the presence of intr-remapping.
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*
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* For both level and edge triggered, irq migration is a simple atomic
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* update(of vector and cpu destination) of IRTE and flush the hardware cache.
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*
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* For level triggered, we eliminate the io-apic RTE modification (with the
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* updated vector information), by using a virtual vector (io-apic pin number).
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* Real vector that is used for interrupting cpu will be coming from
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* the interrupt-remapping table entry.
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*
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* As the migration is a simple atomic update of IRTE, the same mechanism
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* is used to migrate MSI irq's in the presence of interrupt-remapping.
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*/
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static int
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intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
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bool force)
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{
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struct irq_cfg *cfg = irqd_cfg(data);
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unsigned int dest, irq = data->irq;
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struct irte irte;
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int err;
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if (get_irte(irq, &irte))
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return -EBUSY;
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err = assign_irq_vector(irq, cfg, mask);
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if (err)
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return err;
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err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
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if (err) {
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if (assign_irq_vector(irq, cfg, data->affinity))
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pr_err("Failed to recover vector for irq %d\n", irq);
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return err;
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}
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irte.vector = cfg->vector;
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irte.dest_id = IRTE_DEST(dest);
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/*
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* Atomically updates the IRTE with the new destination, vector
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* and flushes the interrupt entry cache.
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*/
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modify_irte(irq_2_iommu(irq), &irte);
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/*
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* After this point, all the interrupts will start arriving
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* at the new destination. So, time to cleanup the previous
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* vector allocation.
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*/
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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cpumask_copy(data->affinity, mask);
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return 0;
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}
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static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
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{
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struct intel_iommu *iommu = NULL;
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@ -1135,9 +953,6 @@ struct irq_remap_ops intel_irq_remap_ops = {
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.disable = disable_irq_remapping,
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.reenable = reenable_irq_remapping,
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.enable_faulting = enable_drhd_fault_handling,
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.setup_ioapic_entry = intel_setup_ioapic_entry,
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.set_affinity = intel_ioapic_set_affinity,
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.free_irq = free_irte,
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.get_ir_irq_domain = intel_get_ir_irq_domain,
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.get_irq_domain = intel_get_irq_domain,
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};
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