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RISC-V config for v6.12
Two patches, enabling clock and pinctrl support in defconfig for Sopghgo devices. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZuDAZwAKCRB4tDGHoIJi 0pMkAQCnzUqAlnSbaXlAMvnTvAA370PysOIOYIg5fiUC45LqGwD9ELhGn7w2+BGe yHUYieCn70X00cl+DJSB2Boa06gd4QQ= =jq6X -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbhXPEACgkQYKtH/8kJ UidjzQ//UTUxupOLz1XHg7cGj/75WBsVcuQA3e7KXRV1OwNJ3PeJGOufFB1XZcKF bF+oRUR3jARFrpSoQFvCjxpl4Q7fFVXsGC312F2amFTs0DYK+mpkFhLd0uO3PJYB jQ5IDdasSboSiMl4j8TiAFxqGPM3kOPZzX3+KtLzlZJzm9U2excYagg2wiJ66Z7b CtPCV0yDHYR06HhSnHFW2BYlPV1r1U+dtC59/eWq9ucb3ItrSlcaiD9eS6iHVo7E 3QUFcMfcgEJ9yOZ27BmESZFbw4ZsB6eYdK39RTHmy9I3LzbvLp57AgPGh461tuAR s4PmqN4Jd0u+RbTCmAI9CCDM4Vy1qvocvp9HXDwJa5NJx87YiQee1hYu2wuni+0I W5/202tAwfqMHtFm/bn9JG62rOiD0jNFYLDmJ8CILJ8bv4b5VfmEvKUqE0w0pNYD DxGKlEOKFyNOl3P62o3OtbtQhNWmDdZrZuBrOw8Bl9dsoKjxTmq9S5lrAUii6NMv gTU1J1af1ONyk/IFXB+20q6u24q7FUnIDSCgevMzDPNDOZPLloA60PinA60daGCn ZWMiAa5WWNSi2TMBYa1Ve8hs017YC0bBBYSPY5VUMRC3emItEmYF2nExzZcMIqFE YUtxXzoOYfVOnSN+ShYe5fwa3d+xP5g4rs5JNRvWFVCIjZfyQfU= =Ihjw -----END PGP SIGNATURE----- Merge tag 'riscv-config-for-v6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/defconfig RISC-V config for v6.12 Two patches, enabling clock and pinctrl support in defconfig for Sopghgo devices. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-config-for-v6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: defconfig: Enable pinctrl support for CV18XX Series SoC riscv: defconfig: sophgo: enable clks for sg2042 Link: https://lore.kernel.org/r/20240910-annex-ravage-07d63041a7c5@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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commit
3c557d0062
@ -167,6 +167,10 @@ CONFIG_SPI_RSPI=m
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CONFIG_SPI_SIFIVE=y
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CONFIG_SPI_SUN6I=y
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# CONFIG_PTP_1588_CLOCK is not set
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CONFIG_PINCTRL_SOPHGO_CV1800B=y
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CONFIG_PINCTRL_SOPHGO_CV1812H=y
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CONFIG_PINCTRL_SOPHGO_SG2000=y
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CONFIG_PINCTRL_SOPHGO_SG2002=y
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CONFIG_GPIO_SIFIVE=y
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CONFIG_POWER_RESET_GPIO_RESTART=y
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CONFIG_SENSORS_SFCTEMP=m
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@ -249,6 +253,9 @@ CONFIG_VIRTIO_BALLOON=y
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CONFIG_VIRTIO_INPUT=y
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CONFIG_VIRTIO_MMIO=y
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CONFIG_CLK_SOPHGO_CV1800=y
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CONFIG_CLK_SOPHGO_SG2042_PLL=y
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CONFIG_CLK_SOPHGO_SG2042_CLKGEN=y
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CONFIG_CLK_SOPHGO_SG2042_RPGATE=y
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CONFIG_SUN8I_DE2_CCU=m
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CONFIG_RENESAS_OSTM=y
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CONFIG_SUN50I_IOMMU=y
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