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drm/amdgpu: fix bug mclk can't change on Polaris

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the root cause is we gate the clock to uvd vcpu.
mclk's change should need the response from uvd if
it is power on.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2016-11-23 18:09:22 +08:00 committed by Alex Deucher
parent 805b3ba87d
commit 3c3a7e616c
2 changed files with 8 additions and 3 deletions
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6
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
View File

@ -640,7 +640,7 @@ static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
UVD_SUVD_CGC_GATE__SDB_MASK;
if (enable) {
data3 |= (UVD_CGC_GATE__SYS_MASK |
data3 |= (UVD_CGC_GATE__SYS_MASK |
UVD_CGC_GATE__UDEC_MASK |
UVD_CGC_GATE__MPEG2_MASK |
UVD_CGC_GATE__RBC_MASK |
@ -656,9 +656,11 @@ static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
UVD_CGC_GATE__UDEC_DB_MASK |
UVD_CGC_GATE__UDEC_MP_MASK |
UVD_CGC_GATE__WCB_MASK |
UVD_CGC_GATE__VCPU_MASK |
UVD_CGC_GATE__JPEG_MASK |
UVD_CGC_GATE__SCPU_MASK);
/* only in pg enabled, we can gate clock to vcpu*/
if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
data3 |= UVD_CGC_GATE__VCPU_MASK;
data3 &= ~UVD_CGC_GATE__REGS_MASK;
data1 |= suvd_flags;
} else {

5
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
View File

@ -879,10 +879,13 @@ static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
UVD_CGC_GATE__UDEC_DB_MASK |
UVD_CGC_GATE__UDEC_MP_MASK |
UVD_CGC_GATE__WCB_MASK |
UVD_CGC_GATE__VCPU_MASK |
UVD_CGC_GATE__JPEG_MASK |
UVD_CGC_GATE__SCPU_MASK |
UVD_CGC_GATE__JPEG2_MASK);
/* only in pg enabled, we can gate clock to vcpu*/
if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
data3 |= UVD_CGC_GATE__VCPU_MASK;
data3 &= ~UVD_CGC_GATE__REGS_MASK;
} else {
data3 = 0;