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ARM: EXYNOS4: Update Timer part
This patch updates Timer part of EXYNOS4 according to the change of ARCH name, EXYNOS4. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -1,7 +1,7 @@
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/* linux/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
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/* linux/arch/arm/mach-exynos4/include/mach/pwm-clock.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -10,7 +10,7 @@
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*
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* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
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*
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* S5PV310 - pwm clock and timer support
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* EXYNOS4 - pwm clock and timer support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -1,4 +1,4 @@
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/* linux/arch/arm/mach-s5pv310/localtimer.c
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/* linux/arch/arm/mach-exynos4/localtimer.c
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*
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* Cloned from linux/arch/arm/mach-realview/localtimer.c
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*
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@ -1,9 +1,9 @@
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/* linux/arch/arm/mach-s5pv310/time.c
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/* linux/arch/arm/mach-exynos4/time.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5PV310 (and compatible) HRT support
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* EXYNOS4 (and compatible) HRT support
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* PWM 2/4 is used for this feature
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*
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* This program is free software; you can redistribute it and/or modify
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@ -33,7 +33,7 @@ static struct clk *tdiv2;
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static struct clk *tdiv4;
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static struct clk *timerclk;
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static void s5pv310_pwm_stop(unsigned int pwm_id)
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static void exynos4_pwm_stop(unsigned int pwm_id)
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{
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unsigned long tcon;
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@ -52,7 +52,7 @@ static void s5pv310_pwm_stop(unsigned int pwm_id)
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__raw_writel(tcon, S3C2410_TCON);
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}
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static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
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static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
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{
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unsigned long tcon;
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@ -86,7 +86,7 @@ static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
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}
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}
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static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic)
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static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
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{
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unsigned long tcon;
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@ -117,23 +117,23 @@ static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic)
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__raw_writel(tcon, S3C2410_TCON);
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}
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static int s5pv310_pwm_set_next_event(unsigned long cycles,
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static int exynos4_pwm_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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s5pv310_pwm_init(2, cycles);
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s5pv310_pwm_start(2, 0);
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exynos4_pwm_init(2, cycles);
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exynos4_pwm_start(2, 0);
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return 0;
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}
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static void s5pv310_pwm_set_mode(enum clock_event_mode mode,
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static void exynos4_pwm_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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s5pv310_pwm_stop(2);
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exynos4_pwm_stop(2);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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s5pv310_pwm_init(2, clock_count_per_tick);
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s5pv310_pwm_start(2, 1);
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exynos4_pwm_init(2, clock_count_per_tick);
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exynos4_pwm_start(2, 1);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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break;
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@ -149,11 +149,11 @@ static struct clock_event_device pwm_event_device = {
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.rating = 200,
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.shift = 32,
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.set_next_event = s5pv310_pwm_set_next_event,
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.set_mode = s5pv310_pwm_set_mode,
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.set_next_event = exynos4_pwm_set_next_event,
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.set_mode = exynos4_pwm_set_mode,
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};
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irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id)
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irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &pwm_event_device;
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@ -162,13 +162,13 @@ irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static struct irqaction s5pv310_clock_event_irq = {
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static struct irqaction exynos4_clock_event_irq = {
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.name = "pwm_timer2_irq",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = s5pv310_clock_event_isr,
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.handler = exynos4_clock_event_isr,
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};
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static void __init s5pv310_clockevent_init(void)
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static void __init exynos4_clockevent_init(void)
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{
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unsigned long pclk;
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unsigned long clock_rate;
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@ -198,10 +198,10 @@ static void __init s5pv310_clockevent_init(void)
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pwm_event_device.cpumask = cpumask_of(0);
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clockevents_register_device(&pwm_event_device);
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setup_irq(IRQ_TIMER2, &s5pv310_clock_event_irq);
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setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
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}
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static cycle_t s5pv310_pwm4_read(struct clocksource *cs)
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static cycle_t exynos4_pwm4_read(struct clocksource *cs)
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{
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return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
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}
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@ -209,12 +209,12 @@ static cycle_t s5pv310_pwm4_read(struct clocksource *cs)
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struct clocksource pwm_clocksource = {
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.name = "pwm_timer4",
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.rating = 250,
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.read = s5pv310_pwm4_read,
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.read = exynos4_pwm4_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS ,
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};
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static void __init s5pv310_clocksource_init(void)
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static void __init exynos4_clocksource_init(void)
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{
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unsigned long pclk;
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unsigned long clock_rate;
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@ -226,14 +226,14 @@ static void __init s5pv310_clocksource_init(void)
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clock_rate = clk_get_rate(tin4);
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s5pv310_pwm_init(4, ~0);
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s5pv310_pwm_start(4, 1);
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exynos4_pwm_init(4, ~0);
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exynos4_pwm_start(4, 1);
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if (clocksource_register_hz(&pwm_clocksource, clock_rate))
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panic("%s: can't register clocksource\n", pwm_clocksource.name);
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}
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static void __init s5pv310_timer_resources(void)
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static void __init exynos4_timer_resources(void)
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{
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struct platform_device tmpdev;
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@ -267,17 +267,17 @@ static void __init s5pv310_timer_resources(void)
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clk_enable(tin4);
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}
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static void __init s5pv310_timer_init(void)
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static void __init exynos4_timer_init(void)
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{
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#ifdef CONFIG_LOCAL_TIMERS
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twd_base = S5P_VA_TWD;
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#endif
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s5pv310_timer_resources();
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s5pv310_clockevent_init();
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s5pv310_clocksource_init();
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exynos4_timer_resources();
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exynos4_clockevent_init();
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exynos4_clocksource_init();
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}
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struct sys_timer s5pv310_timer = {
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.init = s5pv310_timer_init,
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struct sys_timer exynos4_timer = {
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.init = exynos4_timer_init,
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};
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