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stmmac: update normal descriptor structure (v2)
This patch updates the normal descriptor structure to work fine on new GMAC Synopsys chips. Normal descriptors were designed on the old MAC10/100 databook 1.91 where some bits were reserved: for example the tx checksum insertion and rx checksum offload. The patch maintains the back-compatibility with old MAC devices (tested on STx7109 MAC10/100) and adds new fields that actually new GMAC devices can use. For example, STx7109 (MAC10/100) will pass from the platform tx_coe = 0, enh_desc = 0, has_gmac = 0. A platform like Loongson1B (GMAC) will pass: tx_coe = 1, enh_desc = 0, has_gmac = 1. Thanks to Kelvin, he enhanced the normal descriptors for GMAC (on MIPS Loongson1B platform). Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -49,7 +49,7 @@ struct stmmac_extra_stats {
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unsigned long tx_underflow ____cacheline_aligned;
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unsigned long tx_carrier;
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unsigned long tx_losscarrier;
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unsigned long tx_heartbeat;
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unsigned long vlan_tag;
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unsigned long tx_deferred;
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unsigned long tx_vlan;
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unsigned long tx_jabber;
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@ -58,9 +58,9 @@ struct stmmac_extra_stats {
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unsigned long tx_ip_header_error;
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/* Receive errors */
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unsigned long rx_desc;
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unsigned long rx_partial;
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unsigned long rx_runt;
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unsigned long rx_toolong;
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unsigned long sa_filter_fail;
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unsigned long overflow_error;
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unsigned long ipc_csum_error;
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unsigned long rx_collision;
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unsigned long rx_crc;
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unsigned long rx_length;
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@ -25,33 +25,34 @@ struct dma_desc {
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union {
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struct {
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/* RDES0 */
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u32 reserved1:1;
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u32 payload_csum_error:1;
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u32 crc_error:1;
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u32 dribbling:1;
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u32 mii_error:1;
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u32 receive_watchdog:1;
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u32 frame_type:1;
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u32 collision:1;
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u32 frame_too_long:1;
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u32 ipc_csum_error:1;
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u32 last_descriptor:1;
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u32 first_descriptor:1;
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u32 multicast_frame:1;
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u32 run_frame:1;
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u32 vlan_tag:1;
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u32 overflow_error:1;
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u32 length_error:1;
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u32 partial_frame_error:1;
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u32 sa_filter_fail:1;
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u32 descriptor_error:1;
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u32 error_summary:1;
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u32 frame_length:14;
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u32 filtering_fail:1;
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u32 da_filter_fail:1;
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u32 own:1;
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/* RDES1 */
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u32 buffer1_size:11;
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u32 buffer2_size:11;
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u32 reserved2:2;
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u32 reserved1:2;
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u32 second_address_chained:1;
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u32 end_ring:1;
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u32 reserved3:5;
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u32 reserved2:5;
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u32 disable_ic:1;
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} rx;
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struct {
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/* RDES0 */
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@ -91,24 +92,28 @@ struct dma_desc {
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u32 underflow_error:1;
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u32 excessive_deferral:1;
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u32 collision_count:4;
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u32 heartbeat_fail:1;
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u32 vlan_frame:1;
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u32 excessive_collisions:1;
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u32 late_collision:1;
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u32 no_carrier:1;
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u32 loss_carrier:1;
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u32 reserved1:3;
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u32 payload_error:1;
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u32 frame_flushed:1;
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u32 jabber_timeout:1;
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u32 error_summary:1;
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u32 reserved2:15;
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u32 ip_header_error:1;
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u32 time_stamp_status:1;
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u32 reserved1:13;
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u32 own:1;
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/* TDES1 */
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u32 buffer1_size:11;
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u32 buffer2_size:11;
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u32 reserved3:1;
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u32 time_stamp_enable:1;
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u32 disable_padding:1;
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u32 second_address_chained:1;
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u32 end_ring:1;
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u32 crc_disable:1;
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u32 reserved4:2;
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u32 checksum_insertion:2;
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u32 first_segment:1;
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u32 last_segment:1;
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u32 interrupt:1;
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@ -50,11 +50,12 @@ static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x,
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stats->collisions += p->des01.tx.collision_count;
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ret = -1;
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}
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if (unlikely(p->des01.tx.heartbeat_fail)) {
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x->tx_heartbeat++;
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stats->tx_heartbeat_errors++;
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ret = -1;
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if (p->des01.etx.vlan_frame) {
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CHIP_DBG(KERN_INFO "GMAC TX status: VLAN frame\n");
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x->tx_vlan++;
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}
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if (unlikely(p->des01.tx.deferred))
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x->tx_deferred++;
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@ -68,12 +69,12 @@ static int ndesc_get_tx_len(struct dma_desc *p)
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/* This function verifies if each incoming frame has some errors
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* and, if required, updates the multicast statistics.
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* In case of success, it returns csum_none because the device
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* is not able to compute the csum in HW. */
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* In case of success, it returns good_frame because the GMAC device
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* is supposed to be able to compute the csum in HW. */
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static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p)
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{
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int ret = csum_none;
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int ret = good_frame;
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struct net_device_stats *stats = (struct net_device_stats *)data;
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if (unlikely(p->des01.rx.last_descriptor == 0)) {
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@ -86,12 +87,12 @@ static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
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if (unlikely(p->des01.rx.error_summary)) {
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if (unlikely(p->des01.rx.descriptor_error))
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x->rx_desc++;
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if (unlikely(p->des01.rx.partial_frame_error))
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x->rx_partial++;
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if (unlikely(p->des01.rx.run_frame))
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x->rx_runt++;
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if (unlikely(p->des01.rx.frame_too_long))
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x->rx_toolong++;
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if (unlikely(p->des01.rx.sa_filter_fail))
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x->sa_filter_fail++;
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if (unlikely(p->des01.rx.overflow_error))
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x->overflow_error++;
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if (unlikely(p->des01.rx.ipc_csum_error))
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x->ipc_csum_error++;
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if (unlikely(p->des01.rx.collision)) {
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x->rx_collision++;
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stats->collisions++;
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@ -113,10 +114,10 @@ static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
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x->rx_mii++;
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ret = discard_frame;
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}
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if (p->des01.rx.multicast_frame) {
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x->rx_multicast++;
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stats->multicast++;
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}
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#ifdef STMMAC_VLAN_TAG_USED
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if (p->des01.rx.vlan_tag)
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x->vlan_tag++;
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#endif
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return ret;
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}
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@ -184,6 +185,9 @@ static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
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{
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p->des01.tx.first_segment = is_fs;
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norm_set_tx_desc_len(p, len);
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if (likely(csum_flag))
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p->des01.tx.checksum_insertion = cic_full;
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}
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static void ndesc_clear_tx_ic(struct dma_desc *p)
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@ -50,7 +50,7 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
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STMMAC_STAT(tx_underflow),
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STMMAC_STAT(tx_carrier),
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STMMAC_STAT(tx_losscarrier),
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STMMAC_STAT(tx_heartbeat),
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STMMAC_STAT(vlan_tag),
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STMMAC_STAT(tx_deferred),
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STMMAC_STAT(tx_vlan),
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STMMAC_STAT(rx_vlan),
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@ -59,9 +59,9 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
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STMMAC_STAT(tx_payload_error),
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STMMAC_STAT(tx_ip_header_error),
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STMMAC_STAT(rx_desc),
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STMMAC_STAT(rx_partial),
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STMMAC_STAT(rx_runt),
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STMMAC_STAT(rx_toolong),
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STMMAC_STAT(sa_filter_fail),
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STMMAC_STAT(overflow_error),
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STMMAC_STAT(ipc_csum_error),
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STMMAC_STAT(rx_collision),
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STMMAC_STAT(rx_crc),
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STMMAC_STAT(rx_length),
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@ -813,6 +813,7 @@ static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
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static int stmmac_get_hw_features(struct stmmac_priv *priv)
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{
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u32 hw_cap = 0;
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if (priv->hw->dma->get_hw_feature) {
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hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
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@ -938,6 +939,7 @@ static int stmmac_open(struct net_device *dev)
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stmmac_get_hw_features(priv);
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priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr);
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if (priv->rx_coe)
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pr_info("stmmac: Rx Checksum Offload Engine supported\n");
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if (priv->plat->tx_coe)
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@ -1275,8 +1277,8 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit)
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#endif
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skb->protocol = eth_type_trans(skb, priv->dev);
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if (unlikely(status == csum_none)) {
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/* always for the old mac 10/100 */
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if (unlikely(!priv->rx_coe)) {
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/* No RX COE for old mac10/100 devices */
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skb_checksum_none_assert(skb);
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netif_receive_skb(skb);
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} else {
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