mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-27 22:24:11 +08:00
PCI changes for the v4.1 merge window:
Enumeration
- Read capability list as dwords, not bytes (Sean O. Stalley)
Resource management
- Don't check for PNP overlaps with unassigned PCI BARs (Bjorn Helgaas)
- Mark invalid BARs as unassigned (Bjorn Helgaas)
- Show driver, BAR#, and resource on pci_ioremap_bar() failure (Bjorn Helgaas)
- Fail pci_ioremap_bar() on unassigned resources (Bjorn Helgaas)
- Assign resources before drivers claim devices (Yijing Wang)
- Claim bus resources before pci_bus_add_devices() (Yijing Wang)
Power management
- Optimize device state transition delays (Aaron Lu)
- Don't clear ASPM bits when the FADT declares it's unsupported (Matthew Garrett)
Virtualization
- Add ACS quirks for Intel 1G NICs (Alex Williamson)
IOMMU
- Add ptr to OF node arg to of_iommu_configure() (Murali Karicheri)
- Move of_dma_configure() to device.c to help re-use (Murali Karicheri)
- Fix size when dma-range is not used (Murali Karicheri)
- Add helper functions pci_get[put]_host_bridge_device() (Murali Karicheri)
- Add of_pci_dma_configure() to update DMA configuration (Murali Karicheri)
- Update DMA configuration from DT (Murali Karicheri)
- dma-mapping: limit IOMMU mapping size (Murali Karicheri)
- Calculate device DMA masks based on DT dma-range size (Murali Karicheri)
ARM Versatile host bridge driver
- Check for devm_ioremap_resource() failures (Jisheng Zhang)
Broadcom iProc host bridge driver
- Add Broadcom iProc PCIe driver (Ray Jui)
Marvell MVEBU host bridge driver
- Add suspend/resume support (Thomas Petazzoni)
Renesas R-Car host bridge driver
- Fix position of MSI enable bit (Nobuhiro Iwamatsu)
- Write zeroes to reserved PCIEPARL bits (Nobuhiro Iwamatsu)
- Change PCIEPARL and PCIEPARH to PCIEPALR and PCIEPAUR (Nobuhiro Iwamatsu)
- Verify that mem_res is 64K-aligned (Nobuhiro Iwamatsu)
Samsung Exynos host bridge driver
- Fix INTx enablement statement termination error (Jaehoon Chung)
Miscellaneous
- Make a shareable UUID for PCI firmware ACPI _DSM (Aaron Lu)
- Clarify policy for vendor IDs in pci.txt (Michael S. Tsirkin)
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Merge tag 'pci-v4.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI changes from Bjorn Helgaas:
"Enumeration
- Read capability list as dwords, not bytes (Sean O. Stalley)
Resource management
- Don't check for PNP overlaps with unassigned PCI BARs (Bjorn Helgaas)
- Mark invalid BARs as unassigned (Bjorn Helgaas)
- Show driver, BAR#, and resource on pci_ioremap_bar() failure (Bjorn Helgaas)
- Fail pci_ioremap_bar() on unassigned resources (Bjorn Helgaas)
- Assign resources before drivers claim devices (Yijing Wang)
- Claim bus resources before pci_bus_add_devices() (Yijing Wang)
Power management
- Optimize device state transition delays (Aaron Lu)
- Don't clear ASPM bits when the FADT declares it's unsupported (Matthew Garrett)
Virtualization
- Add ACS quirks for Intel 1G NICs (Alex Williamson)
IOMMU
- Add ptr to OF node arg to of_iommu_configure() (Murali Karicheri)
- Move of_dma_configure() to device.c to help re-use (Murali Karicheri)
- Fix size when dma-range is not used (Murali Karicheri)
- Add helper functions pci_get[put]_host_bridge_device() (Murali Karicheri)
- Add of_pci_dma_configure() to update DMA configuration (Murali Karicheri)
- Update DMA configuration from DT (Murali Karicheri)
- dma-mapping: limit IOMMU mapping size (Murali Karicheri)
- Calculate device DMA masks based on DT dma-range size (Murali Karicheri)
ARM Versatile host bridge driver
- Check for devm_ioremap_resource() failures (Jisheng Zhang)
Broadcom iProc host bridge driver
- Add Broadcom iProc PCIe driver (Ray Jui)
Marvell MVEBU host bridge driver
- Add suspend/resume support (Thomas Petazzoni)
Renesas R-Car host bridge driver
- Fix position of MSI enable bit (Nobuhiro Iwamatsu)
- Write zeroes to reserved PCIEPARL bits (Nobuhiro Iwamatsu)
- Change PCIEPARL and PCIEPARH to PCIEPALR and PCIEPAUR (Nobuhiro Iwamatsu)
- Verify that mem_res is 64K-aligned (Nobuhiro Iwamatsu)
Samsung Exynos host bridge driver
- Fix INTx enablement statement termination error (Jaehoon Chung)
Miscellaneous
- Make a shareable UUID for PCI firmware ACPI _DSM (Aaron Lu)
- Clarify policy for vendor IDs in pci.txt (Michael S. Tsirkin)"
* tag 'pci-v4.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (36 commits)
PCI: Read capability list as dwords, not bytes
PCI: layerscape: Simplify platform_get_resource_byname() failure checking
PCI: keystone: Don't dereference possible NULL pointer
PCI: versatile: Check for devm_ioremap_resource() failures
PCI: Don't clear ASPM bits when the FADT declares it's unsupported
PCI: Clarify policy for vendor IDs in pci.txt
PCI/ACPI: Optimize device state transition delays
PCI: Export pci_find_host_bridge() for use inside PCI core
PCI: Make a shareable UUID for PCI firmware ACPI _DSM
PCI: Fix typo in Thunderbolt kernel message
PCI: exynos: Fix INTx enablement statement termination error
PCI: iproc: Add Broadcom iProc PCIe support
PCI: iproc: Add DT docs for Broadcom iProc PCIe driver
PCI: Export symbols required for loadable host driver modules
PCI: Add ACS quirks for Intel 1G NICs
PCI: mvebu: Add suspend/resume support
PCI: Cleanup control flow
sparc/PCI: Claim bus resources before pci_bus_add_devices()
PCI: Assign resources before drivers claim devices (pci_scan_root_bus())
PCI: Fail pci_ioremap_bar() on unassigned resources
...
This commit is contained in:
Linus Torvalds
commit
3be1b98e07
@ -564,14 +564,14 @@ to be handled by platform and generic code, not individual drivers.
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8. Vendor and device identifications
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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One is not required to add new device ids to include/linux/pci_ids.h.
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Please add PCI_VENDOR_ID_xxx for vendors and a hex constant for device ids.
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Do not add new device or vendor IDs to include/linux/pci_ids.h unless they
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are shared across multiple drivers. You can add private definitions in
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your driver if they're helpful, or just use plain hex constants.
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PCI_VENDOR_ID_xxx constants are re-used. The device ids are arbitrary
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hex numbers (vendor controlled) and normally used only in a single
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location, the pci_device_id table.
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The device IDs are arbitrary hex numbers (vendor controlled) and normally used
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only in a single location, the pci_device_id table.
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Please DO submit new vendor/device ids to pciids.sourceforge.net project.
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Please DO submit new vendor/device IDs to http://pciids.sourceforge.net/.
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63
Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
Normal file
63
Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
Normal file
@ -0,0 +1,63 @@
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* Broadcom iProc PCIe controller with the platform bus interface
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Required properties:
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- compatible: Must be "brcm,iproc-pcie"
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- reg: base address and length of the PCIe controller I/O register space
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- #interrupt-cells: set to <1>
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- interrupt-map-mask and interrupt-map, standard PCI properties to define the
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mapping of the PCIe interface to interrupt numbers
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- linux,pci-domain: PCI domain ID. Should be unique for each host controller
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- bus-range: PCI bus numbers covered
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- device_type: set to "pci"
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- ranges: ranges for the PCI memory and I/O regions
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Optional properties:
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- phys: phandle of the PCIe PHY device
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- phy-names: must be "pcie-phy"
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Example:
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pcie0: pcie@18012000 {
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compatible = "brcm,iproc-pcie";
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reg = <0x18012000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x28000000 0 0x00010000
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0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
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phys = <&phy 0 5>;
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phy-names = "pcie-phy";
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};
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pcie1: pcie@18013000 {
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compatible = "brcm,iproc-pcie";
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reg = <0x18013000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
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linux,pci-domain = <1>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x48000000 0 0x00010000
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0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
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phys = <&phy 1 6>;
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phy-names = "pcie-phy";
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};
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@ -338,6 +338,8 @@ common_init_pci(void)
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bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops,
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hose, &resources);
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if (!bus)
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continue;
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hose->bus = bus;
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hose->need_domain_info = need_domain_info;
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next_busno = bus->busn_res.end + 1;
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@ -353,6 +355,11 @@ common_init_pci(void)
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pci_assign_unassigned_resources();
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pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
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for (hose = hose_head; hose; hose = hose->next) {
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bus = hose->bus;
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if (bus)
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pci_bus_add_devices(bus);
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}
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}
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@ -207,6 +207,9 @@ nautilus_init_pci(void)
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/* Scan our single hose. */
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bus = pci_scan_bus(0, alpha_mv.pci_ops, hose);
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if (!bus)
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return;
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hose->bus = bus;
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pcibios_claim_one_bus(bus);
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@ -253,6 +256,7 @@ nautilus_init_pci(void)
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for the root bus, so just clear it. */
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bus->self = NULL;
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pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
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pci_bus_add_devices(bus);
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}
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/*
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@ -155,17 +155,13 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
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static struct pci_bus __init *
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dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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{
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struct pci_bus *bus;
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if (nr < num_pcie_ports) {
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bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
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&sys->resources);
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} else {
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bus = NULL;
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if (nr >= num_pcie_ports) {
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BUG();
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return NULL;
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}
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return bus;
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return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
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&sys->resources);
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}
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static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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@ -197,17 +197,13 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
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static struct pci_bus __init *
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mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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{
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struct pci_bus *bus;
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if (nr < num_pcie_ports) {
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bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
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&sys->resources);
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} else {
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bus = NULL;
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if (nr >= num_pcie_ports) {
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BUG();
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return NULL;
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}
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return bus;
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return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
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&sys->resources);
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}
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static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot,
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@ -540,37 +540,33 @@ void __init orion5x_pci_set_cardbus_mode(void)
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int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
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{
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int ret = 0;
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vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
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if (nr == 0) {
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orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
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ret = pcie_setup(sys);
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} else if (nr == 1 && !orion5x_pci_disabled) {
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orion5x_pci_set_bus_nr(sys->busnr);
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ret = pci_setup(sys);
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return pcie_setup(sys);
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}
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return ret;
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if (nr == 1 && !orion5x_pci_disabled) {
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orion5x_pci_set_bus_nr(sys->busnr);
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return pci_setup(sys);
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}
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return 0;
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}
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struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
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{
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struct pci_bus *bus;
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if (nr == 0)
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return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
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&sys->resources);
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if (nr == 0) {
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bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
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&sys->resources);
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} else if (nr == 1 && !orion5x_pci_disabled) {
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bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys,
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&sys->resources);
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} else {
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bus = NULL;
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BUG();
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}
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if (nr == 1 && !orion5x_pci_disabled)
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return pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys,
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&sys->resources);
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return bus;
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BUG();
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return NULL;
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}
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int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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@ -2027,6 +2027,13 @@ static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
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if (!iommu)
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return false;
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/*
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* currently arm_iommu_create_mapping() takes a max of size_t
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* for size param. So check this limit for now.
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*/
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if (size > SIZE_MAX)
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return false;
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mapping = arm_iommu_create_mapping(dev->bus, dma_base, size);
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if (IS_ERR(mapping)) {
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pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n",
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@ -316,6 +316,7 @@ void pcibios_fixup_bus(struct pci_bus *bus)
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int __init pcibios_init(void)
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{
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struct pci_bus *bus;
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struct pci_ops *dir = NULL;
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LIST_HEAD(resources);
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@ -383,12 +384,15 @@ int __init pcibios_init(void)
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printk("PCI: Probing PCI hardware\n");
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pci_add_resource(&resources, &pci_ioport_resource);
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pci_add_resource(&resources, &pci_iomem_resource);
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pci_scan_root_bus(NULL, 0, pci_root_ops, NULL, &resources);
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bus = pci_scan_root_bus(NULL, 0, pci_root_ops, NULL, &resources);
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pcibios_irq_init();
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pcibios_fixup_irqs();
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pcibios_resource_survey();
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if (!bus)
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return 0;
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pci_bus_add_devices(bus);
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return 0;
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}
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@ -271,7 +271,9 @@ sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
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if (bus == NULL) {
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kfree(res);
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kfree(controller);
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return;
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}
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pci_bus_add_devices(bus);
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}
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/*
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@ -313,12 +313,16 @@ static int __init mcf_pci_init(void)
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schedule_timeout(msecs_to_jiffies(200));
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rootbus = pci_scan_bus(0, &mcf_pci_ops, NULL);
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if (!rootbus)
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return -ENODEV;
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rootbus->resource[0] = &mcf_pci_io;
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rootbus->resource[1] = &mcf_pci_mem;
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pci_fixup_irqs(pci_common_swizzle, mcf_pci_map_irq);
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pci_bus_size_bridges(rootbus);
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pci_bus_assign_resources(rootbus);
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pci_bus_add_devices(rootbus);
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return 0;
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}
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@ -1382,6 +1382,10 @@ static int __init pcibios_init(void)
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/* Call common code to handle resource allocation */
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pcibios_resource_survey();
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
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if (hose->bus)
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pci_bus_add_devices(hose->bus);
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}
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return 0;
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}
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@ -94,27 +94,29 @@ static void pcibios_scanbus(struct pci_controller *hose)
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pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
|
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bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
|
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&resources);
|
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if (!bus)
|
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pci_free_resource_list(&resources);
|
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|
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hose->bus = bus;
|
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|
||||
need_domain_info = need_domain_info || hose->index;
|
||||
hose->need_domain_info = need_domain_info;
|
||||
if (bus) {
|
||||
next_busno = bus->busn_res.end + 1;
|
||||
/* Don't allow 8-bit bus number overflow inside the hose -
|
||||
reserve some space for bridges. */
|
||||
if (next_busno > 224) {
|
||||
next_busno = 0;
|
||||
need_domain_info = 1;
|
||||
}
|
||||
|
||||
if (!pci_has_flag(PCI_PROBE_ONLY)) {
|
||||
pci_bus_size_bridges(bus);
|
||||
pci_bus_assign_resources(bus);
|
||||
}
|
||||
if (!bus) {
|
||||
pci_free_resource_list(&resources);
|
||||
return;
|
||||
}
|
||||
|
||||
next_busno = bus->busn_res.end + 1;
|
||||
/* Don't allow 8-bit bus number overflow inside the hose -
|
||||
reserve some space for bridges. */
|
||||
if (next_busno > 224) {
|
||||
next_busno = 0;
|
||||
need_domain_info = 1;
|
||||
}
|
||||
|
||||
if (!pci_has_flag(PCI_PROBE_ONLY)) {
|
||||
pci_bus_size_bridges(bus);
|
||||
pci_bus_assign_resources(bus);
|
||||
}
|
||||
pci_bus_add_devices(bus);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
||||
@ -342,6 +342,7 @@ static int __init pcibios_init(void)
|
||||
{
|
||||
resource_size_t io_offset, mem_offset;
|
||||
LIST_HEAD(resources);
|
||||
struct pci_bus *bus;
|
||||
|
||||
ioport_resource.start = 0xA0000000;
|
||||
ioport_resource.end = 0xDFFFFFFF;
|
||||
@ -371,11 +372,14 @@ static int __init pcibios_init(void)
|
||||
|
||||
pci_add_resource_offset(&resources, &pci_ioport_resource, io_offset);
|
||||
pci_add_resource_offset(&resources, &pci_iomem_resource, mem_offset);
|
||||
pci_scan_root_bus(NULL, 0, &pci_direct_ampci, NULL, &resources);
|
||||
bus = pci_scan_root_bus(NULL, 0, &pci_direct_ampci, NULL, &resources);
|
||||
if (!bus)
|
||||
return 0;
|
||||
|
||||
pcibios_irq_init();
|
||||
pcibios_fixup_irqs();
|
||||
pcibios_resource_survey();
|
||||
pci_bus_add_devices(bus);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -780,8 +780,8 @@ static int zpci_scan_bus(struct zpci_dev *zdev)
|
||||
zpci_cleanup_bus_resources(zdev);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
zdev->bus->max_bus_speed = zdev->max_bus_speed;
|
||||
pci_bus_add_devices(zdev->bus);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -58,20 +58,23 @@ static void pcibios_scanbus(struct pci_channel *hose)
|
||||
|
||||
need_domain_info = need_domain_info || hose->index;
|
||||
hose->need_domain_info = need_domain_info;
|
||||
if (bus) {
|
||||
next_busno = bus->busn_res.end + 1;
|
||||
/* Don't allow 8-bit bus number overflow inside the hose -
|
||||
reserve some space for bridges. */
|
||||
if (next_busno > 224) {
|
||||
next_busno = 0;
|
||||
need_domain_info = 1;
|
||||
}
|
||||
|
||||
pci_bus_size_bridges(bus);
|
||||
pci_bus_assign_resources(bus);
|
||||
} else {
|
||||
if (!bus) {
|
||||
pci_free_resource_list(&resources);
|
||||
return;
|
||||
}
|
||||
|
||||
next_busno = bus->busn_res.end + 1;
|
||||
/* Don't allow 8-bit bus number overflow inside the hose -
|
||||
reserve some space for bridges. */
|
||||
if (next_busno > 224) {
|
||||
next_busno = 0;
|
||||
need_domain_info = 1;
|
||||
}
|
||||
|
||||
pci_bus_size_bridges(bus);
|
||||
pci_bus_assign_resources(bus);
|
||||
pci_bus_add_devices(bus);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -34,15 +34,17 @@ void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
|
||||
|
||||
root_bus = pci_scan_root_bus(&ofdev->dev, 0, info->ops, info,
|
||||
&resources);
|
||||
if (root_bus) {
|
||||
/* Setup IRQs of all devices using custom routines */
|
||||
pci_fixup_irqs(pci_common_swizzle, info->map_irq);
|
||||
|
||||
/* Assign devices with resources */
|
||||
pci_assign_unassigned_resources();
|
||||
} else {
|
||||
if (!root_bus) {
|
||||
pci_free_resource_list(&resources);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Setup IRQs of all devices using custom routines */
|
||||
pci_fixup_irqs(pci_common_swizzle, info->map_irq);
|
||||
|
||||
/* Assign devices with resources */
|
||||
pci_assign_unassigned_resources();
|
||||
pci_bus_add_devices(root_bus);
|
||||
}
|
||||
|
||||
void pcibios_fixup_bus(struct pci_bus *pbus)
|
||||
|
||||
@ -674,11 +674,10 @@ struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
|
||||
}
|
||||
|
||||
pci_of_scan_bus(pbm, node, bus);
|
||||
pci_bus_add_devices(bus);
|
||||
pci_bus_register_of_sysfs(bus);
|
||||
|
||||
pci_claim_bus_resources(bus);
|
||||
|
||||
pci_bus_add_devices(bus);
|
||||
return bus;
|
||||
}
|
||||
|
||||
|
||||
@ -391,12 +391,16 @@ static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic)
|
||||
struct linux_pbm_info *pbm = &pcic->pbm;
|
||||
|
||||
pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm);
|
||||
if (!pbm->pci_bus)
|
||||
return;
|
||||
|
||||
#if 0 /* deadwood transplanted from sparc64 */
|
||||
pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
|
||||
pci_record_assignments(pbm, pbm->pci_bus);
|
||||
pci_assign_unassigned(pbm, pbm->pci_bus);
|
||||
pci_fixup_irq(pbm, pbm->pci_bus);
|
||||
#endif
|
||||
pci_bus_add_devices(pbm->pci_bus);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -339,6 +339,8 @@ int __init pcibios_init(void)
|
||||
struct pci_bus *next_bus;
|
||||
struct pci_dev *dev;
|
||||
|
||||
pci_bus_add_devices(root_bus);
|
||||
|
||||
list_for_each_entry(dev, &root_bus->devices, bus_list) {
|
||||
/*
|
||||
* Find the PCI host controller, ie. the 1st
|
||||
|
||||
@ -1030,6 +1030,8 @@ int __init pcibios_init(void)
|
||||
alloc_mem_map_failed:
|
||||
break;
|
||||
}
|
||||
|
||||
pci_bus_add_devices(root_bus);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -266,17 +266,10 @@ static int __init pci_common_init(void)
|
||||
pci_fixup_irqs(pci_common_swizzle, pci_puv3_map_irq);
|
||||
|
||||
if (!pci_has_flag(PCI_PROBE_ONLY)) {
|
||||
/*
|
||||
* Size the bridge windows.
|
||||
*/
|
||||
pci_bus_size_bridges(puv3_bus);
|
||||
|
||||
/*
|
||||
* Assign resources.
|
||||
*/
|
||||
pci_bus_assign_resources(puv3_bus);
|
||||
}
|
||||
|
||||
pci_bus_add_devices(puv3_bus);
|
||||
return 0;
|
||||
}
|
||||
subsys_initcall(pci_common_init);
|
||||
|
||||
@ -490,7 +490,9 @@ void pcibios_scan_root(int busnum)
|
||||
if (!bus) {
|
||||
pci_free_resource_list(&resources);
|
||||
kfree(sd);
|
||||
return;
|
||||
}
|
||||
pci_bus_add_devices(bus);
|
||||
}
|
||||
|
||||
void __init pcibios_set_cache_line_size(void)
|
||||
|
||||
@ -174,7 +174,7 @@ static int __init pcibios_init(void)
|
||||
struct pci_controller *pci_ctrl;
|
||||
struct list_head resources;
|
||||
struct pci_bus *bus;
|
||||
int next_busno = 0;
|
||||
int next_busno = 0, ret;
|
||||
|
||||
printk("PCI: Probing PCI hardware\n");
|
||||
|
||||
@ -185,14 +185,25 @@ static int __init pcibios_init(void)
|
||||
pci_controller_apertures(pci_ctrl, &resources);
|
||||
bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno,
|
||||
pci_ctrl->ops, pci_ctrl, &resources);
|
||||
if (!bus)
|
||||
continue;
|
||||
|
||||
pci_ctrl->bus = bus;
|
||||
pci_ctrl->last_busno = bus->busn_res.end;
|
||||
if (next_busno <= pci_ctrl->last_busno)
|
||||
next_busno = pci_ctrl->last_busno+1;
|
||||
}
|
||||
pci_bus_count = next_busno;
|
||||
ret = platform_pcibios_fixup();
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return platform_pcibios_fixup();
|
||||
for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
|
||||
if (pci_ctrl->bus)
|
||||
pci_bus_add_devices(pci_ctrl->bus);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
subsys_initcall(pcibios_init);
|
||||
|
||||
@ -423,8 +423,7 @@ out:
|
||||
}
|
||||
EXPORT_SYMBOL(acpi_pci_osc_control_set);
|
||||
|
||||
static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
|
||||
int *clear_aspm)
|
||||
static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
|
||||
{
|
||||
u32 support, control, requested;
|
||||
acpi_status status;
|
||||
@ -495,10 +494,12 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
|
||||
decode_osc_control(root, "OS now controls", control);
|
||||
if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
|
||||
/*
|
||||
* We have ASPM control, but the FADT indicates
|
||||
* that it's unsupported. Clear it.
|
||||
* We have ASPM control, but the FADT indicates that
|
||||
* it's unsupported. Leave existing configuration
|
||||
* intact and prevent the OS from touching it.
|
||||
*/
|
||||
*clear_aspm = 1;
|
||||
dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n");
|
||||
*no_aspm = 1;
|
||||
}
|
||||
} else {
|
||||
decode_osc_control(root, "OS requested", requested);
|
||||
@ -525,7 +526,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
|
||||
int result;
|
||||
struct acpi_pci_root *root;
|
||||
acpi_handle handle = device->handle;
|
||||
int no_aspm = 0, clear_aspm = 0;
|
||||
int no_aspm = 0;
|
||||
bool hotadd = system_state != SYSTEM_BOOTING;
|
||||
|
||||
root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
|
||||
@ -584,7 +585,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
|
||||
|
||||
root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle);
|
||||
|
||||
negotiate_os_control(root, &no_aspm, &clear_aspm);
|
||||
negotiate_os_control(root, &no_aspm);
|
||||
|
||||
/*
|
||||
* TBD: Need PCI interface for enumeration/configuration of roots.
|
||||
@ -607,10 +608,6 @@ static int acpi_pci_root_add(struct acpi_device *device,
|
||||
goto remove_dmar;
|
||||
}
|
||||
|
||||
if (clear_aspm) {
|
||||
dev_info(&device->dev, "Disabling ASPM (FADT indicates it is unsupported)\n");
|
||||
pcie_clear_aspm(root->bus);
|
||||
}
|
||||
if (no_aspm)
|
||||
pcie_no_aspm();
|
||||
|
||||
|
||||
@ -133,19 +133,25 @@ struct iommu_ops *of_iommu_get_ops(struct device_node *np)
|
||||
return ops;
|
||||
}
|
||||
|
||||
struct iommu_ops *of_iommu_configure(struct device *dev)
|
||||
struct iommu_ops *of_iommu_configure(struct device *dev,
|
||||
struct device_node *master_np)
|
||||
{
|
||||
struct of_phandle_args iommu_spec;
|
||||
struct device_node *np;
|
||||
struct iommu_ops *ops = NULL;
|
||||
int idx = 0;
|
||||
|
||||
if (dev_is_pci(dev)) {
|
||||
dev_err(dev, "IOMMU is currently not supported for PCI\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* We don't currently walk up the tree looking for a parent IOMMU.
|
||||
* See the `Notes:' section of
|
||||
* Documentation/devicetree/bindings/iommu/iommu.txt
|
||||
*/
|
||||
while (!of_parse_phandle_with_args(dev->of_node, "iommus",
|
||||
while (!of_parse_phandle_with_args(master_np, "iommus",
|
||||
"#iommu-cells", idx,
|
||||
&iommu_spec)) {
|
||||
np = iommu_spec.np;
|
||||
|
||||
@ -2,6 +2,9 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_iommu.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
@ -66,6 +69,87 @@ int of_device_add(struct platform_device *ofdev)
|
||||
return device_add(&ofdev->dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* of_dma_configure - Setup DMA configuration
|
||||
* @dev: Device to apply DMA configuration
|
||||
* @np: Pointer to OF node having DMA configuration
|
||||
*
|
||||
* Try to get devices's DMA configuration from DT and update it
|
||||
* accordingly.
|
||||
*
|
||||
* If platform code needs to use its own special DMA configuration, it
|
||||
* can use a platform bus notifier and handle BUS_NOTIFY_ADD_DEVICE events
|
||||
* to fix up DMA configuration.
|
||||
*/
|
||||
void of_dma_configure(struct device *dev, struct device_node *np)
|
||||
{
|
||||
u64 dma_addr, paddr, size;
|
||||
int ret;
|
||||
bool coherent;
|
||||
unsigned long offset;
|
||||
struct iommu_ops *iommu;
|
||||
|
||||
/*
|
||||
* Set default coherent_dma_mask to 32 bit. Drivers are expected to
|
||||
* setup the correct supported mask.
|
||||
*/
|
||||
if (!dev->coherent_dma_mask)
|
||||
dev->coherent_dma_mask = DMA_BIT_MASK(32);
|
||||
|
||||
/*
|
||||
* Set it to coherent_dma_mask by default if the architecture
|
||||
* code has not set it.
|
||||
*/
|
||||
if (!dev->dma_mask)
|
||||
dev->dma_mask = &dev->coherent_dma_mask;
|
||||
|
||||
ret = of_dma_get_range(np, &dma_addr, &paddr, &size);
|
||||
if (ret < 0) {
|
||||
dma_addr = offset = 0;
|
||||
size = dev->coherent_dma_mask + 1;
|
||||
} else {
|
||||
offset = PFN_DOWN(paddr - dma_addr);
|
||||
|
||||
/*
|
||||
* Add a work around to treat the size as mask + 1 in case
|
||||
* it is defined in DT as a mask.
|
||||
*/
|
||||
if (size & 1) {
|
||||
dev_warn(dev, "Invalid size 0x%llx for dma-range\n",
|
||||
size);
|
||||
size = size + 1;
|
||||
}
|
||||
|
||||
if (!size) {
|
||||
dev_err(dev, "Adjusted size 0x%llx invalid\n", size);
|
||||
return;
|
||||
}
|
||||
dev_dbg(dev, "dma_pfn_offset(%#08lx)\n", offset);
|
||||
}
|
||||
|
||||
dev->dma_pfn_offset = offset;
|
||||
|
||||
/*
|
||||
* Limit coherent and dma mask based on size and default mask
|
||||
* set by the driver.
|
||||
*/
|
||||
dev->coherent_dma_mask = min(dev->coherent_dma_mask,
|
||||
DMA_BIT_MASK(ilog2(dma_addr + size)));
|
||||
*dev->dma_mask = min((*dev->dma_mask),
|
||||
DMA_BIT_MASK(ilog2(dma_addr + size)));
|
||||
|
||||
coherent = of_dma_is_coherent(np);
|
||||
dev_dbg(dev, "device is%sdma coherent\n",
|
||||
coherent ? " " : " not ");
|
||||
|
||||
iommu = of_iommu_configure(dev, np);
|
||||
dev_dbg(dev, "device is%sbehind an iommu\n",
|
||||
iommu ? " " : " not ");
|
||||
|
||||
arch_setup_dma_ops(dev, dma_addr, size, iommu, coherent);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_dma_configure);
|
||||
|
||||
int of_device_register(struct platform_device *pdev)
|
||||
{
|
||||
device_initialize(&pdev->dev);
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
#include <linux/export.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
@ -116,6 +117,26 @@ int of_get_pci_domain_nr(struct device_node *node)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_get_pci_domain_nr);
|
||||
|
||||
/**
|
||||
* of_pci_dma_configure - Setup DMA configuration
|
||||
* @dev: ptr to pci_dev struct of the PCI device
|
||||
*
|
||||
* Function to update PCI devices's DMA configuration using the same
|
||||
* info from the OF node of host bridge's parent (if any).
|
||||
*/
|
||||
void of_pci_dma_configure(struct pci_dev *pci_dev)
|
||||
{
|
||||
struct device *dev = &pci_dev->dev;
|
||||
struct device *bridge = pci_get_host_bridge_device(pci_dev);
|
||||
|
||||
if (!bridge->parent)
|
||||
return;
|
||||
|
||||
of_dma_configure(dev, bridge->parent->of_node);
|
||||
pci_put_host_bridge_device(bridge);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_pci_dma_configure);
|
||||
|
||||
#if defined(CONFIG_OF_ADDRESS)
|
||||
/**
|
||||
* of_pci_get_host_bridge_resources - Parse PCI host bridge resources from DT
|
||||
|
||||
@ -19,7 +19,6 @@
|
||||
#include <linux/slab.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_iommu.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
@ -150,59 +149,6 @@ struct platform_device *of_device_alloc(struct device_node *np,
|
||||
}
|
||||
EXPORT_SYMBOL(of_device_alloc);
|
||||
|
||||
/**
|
||||
* of_dma_configure - Setup DMA configuration
|
||||
* @dev: Device to apply DMA configuration
|
||||
*
|
||||
* Try to get devices's DMA configuration from DT and update it
|
||||
* accordingly.
|
||||
*
|
||||
* In case if platform code need to use own special DMA configuration,it
|
||||
* can use Platform bus notifier and handle BUS_NOTIFY_ADD_DEVICE event
|
||||
* to fix up DMA configuration.
|
||||
*/
|
||||
static void of_dma_configure(struct device *dev)
|
||||
{
|
||||
u64 dma_addr, paddr, size;
|
||||
int ret;
|
||||
bool coherent;
|
||||
unsigned long offset;
|
||||
struct iommu_ops *iommu;
|
||||
|
||||
/*
|
||||
* Set default dma-mask to 32 bit. Drivers are expected to setup
|
||||
* the correct supported dma_mask.
|
||||
*/
|
||||
dev->coherent_dma_mask = DMA_BIT_MASK(32);
|
||||
|
||||
/*
|
||||
* Set it to coherent_dma_mask by default if the architecture
|
||||
* code has not set it.
|
||||
*/
|
||||
if (!dev->dma_mask)
|
||||
dev->dma_mask = &dev->coherent_dma_mask;
|
||||
|
||||
ret = of_dma_get_range(dev->of_node, &dma_addr, &paddr, &size);
|
||||
if (ret < 0) {
|
||||
dma_addr = offset = 0;
|
||||
size = dev->coherent_dma_mask;
|
||||
} else {
|
||||
offset = PFN_DOWN(paddr - dma_addr);
|
||||
dev_dbg(dev, "dma_pfn_offset(%#08lx)\n", offset);
|
||||
}
|
||||
dev->dma_pfn_offset = offset;
|
||||
|
||||
coherent = of_dma_is_coherent(dev->of_node);
|
||||
dev_dbg(dev, "device is%sdma coherent\n",
|
||||
coherent ? " " : " not ");
|
||||
|
||||
iommu = of_iommu_configure(dev);
|
||||
dev_dbg(dev, "device is%sbehind an iommu\n",
|
||||
iommu ? " " : " not ");
|
||||
|
||||
arch_setup_dma_ops(dev, dma_addr, size, iommu, coherent);
|
||||
}
|
||||
|
||||
static void of_dma_deconfigure(struct device *dev)
|
||||
{
|
||||
arch_teardown_dma_ops(dev);
|
||||
@ -236,7 +182,7 @@ static struct platform_device *of_platform_device_create_pdata(
|
||||
|
||||
dev->dev.bus = &platform_bus_type;
|
||||
dev->dev.platform_data = platform_data;
|
||||
of_dma_configure(&dev->dev);
|
||||
of_dma_configure(&dev->dev, dev->dev.of_node);
|
||||
|
||||
if (of_device_add(dev) != 0) {
|
||||
of_dma_deconfigure(&dev->dev);
|
||||
@ -299,7 +245,7 @@ static struct amba_device *of_amba_device_create(struct device_node *node,
|
||||
dev_set_name(&dev->dev, "%s", bus_id);
|
||||
else
|
||||
of_device_make_bus_id(&dev->dev);
|
||||
of_dma_configure(&dev->dev);
|
||||
of_dma_configure(&dev->dev, dev->dev.of_node);
|
||||
|
||||
/* Allow the HW Peripheral ID to be overridden */
|
||||
prop = of_get_property(node, "arm,primecell-periphid", NULL);
|
||||
|
||||
@ -16,13 +16,27 @@ static struct pci_bus *find_pci_root_bus(struct pci_bus *bus)
|
||||
return bus;
|
||||
}
|
||||
|
||||
static struct pci_host_bridge *find_pci_host_bridge(struct pci_bus *bus)
|
||||
struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus)
|
||||
{
|
||||
struct pci_bus *root_bus = find_pci_root_bus(bus);
|
||||
|
||||
return to_pci_host_bridge(root_bus->bridge);
|
||||
}
|
||||
|
||||
struct device *pci_get_host_bridge_device(struct pci_dev *dev)
|
||||
{
|
||||
struct pci_bus *root_bus = find_pci_root_bus(dev->bus);
|
||||
struct device *bridge = root_bus->bridge;
|
||||
|
||||
kobject_get(&bridge->kobj);
|
||||
return bridge;
|
||||
}
|
||||
|
||||
void pci_put_host_bridge_device(struct device *dev)
|
||||
{
|
||||
kobject_put(&dev->kobj);
|
||||
}
|
||||
|
||||
void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
|
||||
void (*release_fn)(struct pci_host_bridge *),
|
||||
void *release_data)
|
||||
@ -34,7 +48,7 @@ void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
|
||||
void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
|
||||
struct resource *res)
|
||||
{
|
||||
struct pci_host_bridge *bridge = find_pci_host_bridge(bus);
|
||||
struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
|
||||
struct resource_entry *window;
|
||||
resource_size_t offset = 0;
|
||||
|
||||
@ -59,7 +73,7 @@ static bool region_contains(struct pci_bus_region *region1,
|
||||
void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
|
||||
struct pci_bus_region *region)
|
||||
{
|
||||
struct pci_host_bridge *bridge = find_pci_host_bridge(bus);
|
||||
struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
|
||||
struct resource_entry *window;
|
||||
resource_size_t offset = 0;
|
||||
|
||||
|
||||
@ -106,4 +106,23 @@ config PCI_VERSATILE
|
||||
bool "ARM Versatile PB PCI controller"
|
||||
depends on ARCH_VERSATILE
|
||||
|
||||
config PCIE_IPROC
|
||||
tristate "Broadcom iProc PCIe controller"
|
||||
depends on OF && ARM
|
||||
default n
|
||||
help
|
||||
This enables the iProc PCIe core controller support for Broadcom's
|
||||
iProc family of SoCs. An appropriate bus interface driver also needs
|
||||
to be enabled
|
||||
|
||||
config PCIE_IPROC_PLATFORM
|
||||
tristate "Broadcom iProc PCIe platform bus driver"
|
||||
depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST)
|
||||
depends on OF
|
||||
select PCIE_IPROC
|
||||
default ARCH_BCM_IPROC
|
||||
help
|
||||
Say Y here if you want to use the Broadcom iProc PCIe controller
|
||||
through the generic platform bus interface
|
||||
|
||||
endmenu
|
||||
|
||||
@ -13,3 +13,5 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
|
||||
obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
|
||||
obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
|
||||
obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
|
||||
obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
|
||||
obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
|
||||
|
||||
@ -396,7 +396,7 @@ static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
|
||||
|
||||
/* enable INTX interrupt */
|
||||
val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
|
||||
IRQ_INTC_ASSERT | IRQ_INTD_ASSERT,
|
||||
IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
|
||||
exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
|
||||
}
|
||||
|
||||
|
||||
@ -496,11 +496,12 @@ int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
|
||||
|
||||
/* Index 1 is the application reg. space address */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
ks_pcie->app = *res;
|
||||
ks_pcie->va_app_base = devm_ioremap_resource(pp->dev, res);
|
||||
if (IS_ERR(ks_pcie->va_app_base))
|
||||
return PTR_ERR(ks_pcie->va_app_base);
|
||||
|
||||
ks_pcie->app = *res;
|
||||
|
||||
/* Create legacy IRQ domain */
|
||||
ks_pcie->legacy_irq_domain =
|
||||
irq_domain_add_linear(ks_pcie->legacy_intc_np,
|
||||
|
||||
@ -127,14 +127,11 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
|
||||
pcie->dev = &pdev->dev;
|
||||
|
||||
dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
|
||||
if (!dbi_base) {
|
||||
dev_err(&pdev->dev, "missing *regs* space\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
|
||||
if (IS_ERR(pcie->dbi))
|
||||
if (IS_ERR(pcie->dbi)) {
|
||||
dev_err(&pdev->dev, "missing *regs* space\n");
|
||||
return PTR_ERR(pcie->dbi);
|
||||
}
|
||||
|
||||
pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
|
||||
"fsl,pcie-scfg");
|
||||
|
||||
@ -129,6 +129,7 @@ struct mvebu_pcie_port {
|
||||
size_t memwin_size;
|
||||
phys_addr_t iowin_base;
|
||||
size_t iowin_size;
|
||||
u32 saved_pcie_stat;
|
||||
};
|
||||
|
||||
static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
|
||||
@ -899,6 +900,35 @@ static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
|
||||
pcie->msi->dev = &pcie->pdev->dev;
|
||||
}
|
||||
|
||||
static int mvebu_pcie_suspend(struct device *dev)
|
||||
{
|
||||
struct mvebu_pcie *pcie;
|
||||
int i;
|
||||
|
||||
pcie = dev_get_drvdata(dev);
|
||||
for (i = 0; i < pcie->nports; i++) {
|
||||
struct mvebu_pcie_port *port = pcie->ports + i;
|
||||
port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mvebu_pcie_resume(struct device *dev)
|
||||
{
|
||||
struct mvebu_pcie *pcie;
|
||||
int i;
|
||||
|
||||
pcie = dev_get_drvdata(dev);
|
||||
for (i = 0; i < pcie->nports; i++) {
|
||||
struct mvebu_pcie_port *port = pcie->ports + i;
|
||||
mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
|
||||
mvebu_pcie_setup_hw(port);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mvebu_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct mvebu_pcie *pcie;
|
||||
@ -1056,6 +1086,8 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
|
||||
mvebu_pcie_msi_enable(pcie);
|
||||
mvebu_pcie_enable(pcie);
|
||||
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1068,12 +1100,18 @@ static const struct of_device_id mvebu_pcie_of_match_table[] = {
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
|
||||
|
||||
static struct dev_pm_ops mvebu_pcie_pm_ops = {
|
||||
.suspend_noirq = mvebu_pcie_suspend,
|
||||
.resume_noirq = mvebu_pcie_resume,
|
||||
};
|
||||
|
||||
static struct platform_driver mvebu_pcie_driver = {
|
||||
.driver = {
|
||||
.name = "mvebu-pcie",
|
||||
.of_match_table = mvebu_pcie_of_match_table,
|
||||
/* driver unloading/unbinding currently not supported */
|
||||
.suppress_bind_attrs = true,
|
||||
.pm = &mvebu_pcie_pm_ops,
|
||||
},
|
||||
.probe = mvebu_pcie_probe,
|
||||
};
|
||||
|
||||
@ -301,6 +301,9 @@ static int rcar_pci_probe(struct platform_device *pdev)
|
||||
if (!mem_res || !mem_res->start)
|
||||
return -ENODEV;
|
||||
|
||||
if (mem_res->start & 0xFFFF)
|
||||
return -EINVAL;
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct rcar_pci_priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
|
||||
@ -138,19 +138,19 @@ static int versatile_pci_probe(struct platform_device *pdev)
|
||||
LIST_HEAD(pci_res);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -ENODEV;
|
||||
versatile_pci_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(versatile_pci_base))
|
||||
return PTR_ERR(versatile_pci_base);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
if (!res)
|
||||
return -ENODEV;
|
||||
versatile_cfg_base[0] = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(versatile_cfg_base[0]))
|
||||
return PTR_ERR(versatile_cfg_base[0]);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
|
||||
if (!res)
|
||||
return -ENODEV;
|
||||
versatile_cfg_base[1] = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(versatile_cfg_base[1]))
|
||||
return PTR_ERR(versatile_cfg_base[1]);
|
||||
|
||||
ret = versatile_pci_parse_request_of_pci_ranges(&pdev->dev, &pci_res);
|
||||
if (ret)
|
||||
@ -214,6 +214,7 @@ static int versatile_pci_probe(struct platform_device *pdev)
|
||||
|
||||
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
|
||||
pci_assign_unassigned_bus_resources(bus);
|
||||
pci_bus_add_devices(bus);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
108
drivers/pci/host/pcie-iproc-platform.c
Normal file
108
drivers/pci/host/pcie-iproc-platform.c
Normal file
@ -0,0 +1,108 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/phy/phy.h>
|
||||
|
||||
#include "pcie-iproc.h"
|
||||
|
||||
static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct iproc_pcie *pcie;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct resource reg;
|
||||
resource_size_t iobase = 0;
|
||||
LIST_HEAD(res);
|
||||
int ret;
|
||||
|
||||
pcie = devm_kzalloc(&pdev->dev, sizeof(struct iproc_pcie), GFP_KERNEL);
|
||||
if (!pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
pcie->dev = &pdev->dev;
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
|
||||
ret = of_address_to_resource(np, 0, ®);
|
||||
if (ret < 0) {
|
||||
dev_err(pcie->dev, "unable to obtain controller resources\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pcie->base = devm_ioremap(pcie->dev, reg.start, resource_size(®));
|
||||
if (!pcie->base) {
|
||||
dev_err(pcie->dev, "unable to map controller registers\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* PHY use is optional */
|
||||
pcie->phy = devm_phy_get(&pdev->dev, "pcie-phy");
|
||||
if (IS_ERR(pcie->phy)) {
|
||||
if (PTR_ERR(pcie->phy) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
pcie->phy = NULL;
|
||||
}
|
||||
|
||||
ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &iobase);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev,
|
||||
"unable to get PCI host bridge resources\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pcie->resources = &res;
|
||||
|
||||
ret = iproc_pcie_setup(pcie);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "PCIe controller setup failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int iproc_pcie_pltfm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct iproc_pcie *pcie = platform_get_drvdata(pdev);
|
||||
|
||||
return iproc_pcie_remove(pcie);
|
||||
}
|
||||
|
||||
static const struct of_device_id iproc_pcie_of_match_table[] = {
|
||||
{ .compatible = "brcm,iproc-pcie", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
|
||||
|
||||
static struct platform_driver iproc_pcie_pltfm_driver = {
|
||||
.driver = {
|
||||
.name = "iproc-pcie",
|
||||
.of_match_table = of_match_ptr(iproc_pcie_of_match_table),
|
||||
},
|
||||
.probe = iproc_pcie_pltfm_probe,
|
||||
.remove = iproc_pcie_pltfm_remove,
|
||||
};
|
||||
module_platform_driver(iproc_pcie_pltfm_driver);
|
||||
|
||||
MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
|
||||
MODULE_DESCRIPTION("Broadcom iPROC PCIe platform driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
268
drivers/pci/host/pcie-iproc.c
Normal file
268
drivers/pci/host/pcie-iproc.c
Normal file
@ -0,0 +1,268 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
|
||||
* Copyright (C) 2015 Broadcom Corporatcommon ion
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/msi.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mbus.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/phy/phy.h>
|
||||
|
||||
#include "pcie-iproc.h"
|
||||
|
||||
#define CLK_CONTROL_OFFSET 0x000
|
||||
#define EP_MODE_SURVIVE_PERST_SHIFT 1
|
||||
#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
|
||||
#define RC_PCIE_RST_OUTPUT_SHIFT 0
|
||||
#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
|
||||
|
||||
#define CFG_IND_ADDR_OFFSET 0x120
|
||||
#define CFG_IND_ADDR_MASK 0x00001ffc
|
||||
|
||||
#define CFG_IND_DATA_OFFSET 0x124
|
||||
|
||||
#define CFG_ADDR_OFFSET 0x1f8
|
||||
#define CFG_ADDR_BUS_NUM_SHIFT 20
|
||||
#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
|
||||
#define CFG_ADDR_DEV_NUM_SHIFT 15
|
||||
#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
|
||||
#define CFG_ADDR_FUNC_NUM_SHIFT 12
|
||||
#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
|
||||
#define CFG_ADDR_REG_NUM_SHIFT 2
|
||||
#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
|
||||
#define CFG_ADDR_CFG_TYPE_SHIFT 0
|
||||
#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
|
||||
|
||||
#define CFG_DATA_OFFSET 0x1fc
|
||||
|
||||
#define SYS_RC_INTX_EN 0x330
|
||||
#define SYS_RC_INTX_MASK 0xf
|
||||
|
||||
static inline struct iproc_pcie *sys_to_pcie(struct pci_sys_data *sys)
|
||||
{
|
||||
return sys->private_data;
|
||||
}
|
||||
|
||||
/**
|
||||
* Note access to the configuration registers are protected at the higher layer
|
||||
* by 'pci_lock' in drivers/pci/access.c
|
||||
*/
|
||||
static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
|
||||
unsigned int devfn,
|
||||
int where)
|
||||
{
|
||||
struct pci_sys_data *sys = bus->sysdata;
|
||||
struct iproc_pcie *pcie = sys_to_pcie(sys);
|
||||
unsigned slot = PCI_SLOT(devfn);
|
||||
unsigned fn = PCI_FUNC(devfn);
|
||||
unsigned busno = bus->number;
|
||||
u32 val;
|
||||
|
||||
/* root complex access */
|
||||
if (busno == 0) {
|
||||
if (slot >= 1)
|
||||
return NULL;
|
||||
writel(where & CFG_IND_ADDR_MASK,
|
||||
pcie->base + CFG_IND_ADDR_OFFSET);
|
||||
return (pcie->base + CFG_IND_DATA_OFFSET);
|
||||
}
|
||||
|
||||
if (fn > 1)
|
||||
return NULL;
|
||||
|
||||
/* EP device access */
|
||||
val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
|
||||
(slot << CFG_ADDR_DEV_NUM_SHIFT) |
|
||||
(fn << CFG_ADDR_FUNC_NUM_SHIFT) |
|
||||
(where & CFG_ADDR_REG_NUM_MASK) |
|
||||
(1 & CFG_ADDR_CFG_TYPE_MASK);
|
||||
writel(val, pcie->base + CFG_ADDR_OFFSET);
|
||||
|
||||
return (pcie->base + CFG_DATA_OFFSET);
|
||||
}
|
||||
|
||||
static struct pci_ops iproc_pcie_ops = {
|
||||
.map_bus = iproc_pcie_map_cfg_bus,
|
||||
.read = pci_generic_config_read32,
|
||||
.write = pci_generic_config_write32,
|
||||
};
|
||||
|
||||
static void iproc_pcie_reset(struct iproc_pcie *pcie)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* Configure the PCIe controller as root complex and send a downstream
|
||||
* reset
|
||||
*/
|
||||
val = EP_MODE_SURVIVE_PERST | RC_PCIE_RST_OUTPUT;
|
||||
writel(val, pcie->base + CLK_CONTROL_OFFSET);
|
||||
udelay(250);
|
||||
val &= ~EP_MODE_SURVIVE_PERST;
|
||||
writel(val, pcie->base + CLK_CONTROL_OFFSET);
|
||||
msleep(250);
|
||||
}
|
||||
|
||||
static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
|
||||
{
|
||||
u8 hdr_type;
|
||||
u32 link_ctrl;
|
||||
u16 pos, link_status;
|
||||
int link_is_active = 0;
|
||||
|
||||
/* make sure we are not in EP mode */
|
||||
pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
|
||||
if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
|
||||
dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
|
||||
pci_bus_write_config_word(bus, 0, PCI_CLASS_DEVICE,
|
||||
PCI_CLASS_BRIDGE_PCI);
|
||||
|
||||
/* check link status to see if link is active */
|
||||
pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
|
||||
pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
|
||||
if (link_status & PCI_EXP_LNKSTA_NLW)
|
||||
link_is_active = 1;
|
||||
|
||||
if (!link_is_active) {
|
||||
/* try GEN 1 link speed */
|
||||
#define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
|
||||
#define PCI_TARGET_LINK_SPEED_MASK 0xf
|
||||
#define PCI_TARGET_LINK_SPEED_GEN2 0x2
|
||||
#define PCI_TARGET_LINK_SPEED_GEN1 0x1
|
||||
pci_bus_read_config_dword(bus, 0,
|
||||
PCI_LINK_STATUS_CTRL_2_OFFSET,
|
||||
&link_ctrl);
|
||||
if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
|
||||
PCI_TARGET_LINK_SPEED_GEN2) {
|
||||
link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
|
||||
link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
|
||||
pci_bus_write_config_dword(bus, 0,
|
||||
PCI_LINK_STATUS_CTRL_2_OFFSET,
|
||||
link_ctrl);
|
||||
msleep(100);
|
||||
|
||||
pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
|
||||
pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
|
||||
&link_status);
|
||||
if (link_status & PCI_EXP_LNKSTA_NLW)
|
||||
link_is_active = 1;
|
||||
}
|
||||
}
|
||||
|
||||
dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
|
||||
|
||||
return link_is_active ? 0 : -ENODEV;
|
||||
}
|
||||
|
||||
static void iproc_pcie_enable(struct iproc_pcie *pcie)
|
||||
{
|
||||
writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
|
||||
}
|
||||
|
||||
int iproc_pcie_setup(struct iproc_pcie *pcie)
|
||||
{
|
||||
int ret;
|
||||
struct pci_bus *bus;
|
||||
|
||||
if (!pcie || !pcie->dev || !pcie->base)
|
||||
return -EINVAL;
|
||||
|
||||
if (pcie->phy) {
|
||||
ret = phy_init(pcie->phy);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = phy_power_on(pcie->phy);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "unable to power on PCIe PHY\n");
|
||||
goto err_exit_phy;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
iproc_pcie_reset(pcie);
|
||||
|
||||
pcie->sysdata.private_data = pcie;
|
||||
|
||||
bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops,
|
||||
&pcie->sysdata, pcie->resources);
|
||||
if (!bus) {
|
||||
dev_err(pcie->dev, "unable to create PCI root bus\n");
|
||||
ret = -ENOMEM;
|
||||
goto err_power_off_phy;
|
||||
}
|
||||
pcie->root_bus = bus;
|
||||
|
||||
ret = iproc_pcie_check_link(pcie, bus);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "no PCIe EP device detected\n");
|
||||
goto err_rm_root_bus;
|
||||
}
|
||||
|
||||
iproc_pcie_enable(pcie);
|
||||
|
||||
pci_scan_child_bus(bus);
|
||||
pci_assign_unassigned_bus_resources(bus);
|
||||
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
|
||||
pci_bus_add_devices(bus);
|
||||
|
||||
return 0;
|
||||
|
||||
err_rm_root_bus:
|
||||
pci_stop_root_bus(bus);
|
||||
pci_remove_root_bus(bus);
|
||||
|
||||
err_power_off_phy:
|
||||
if (pcie->phy)
|
||||
phy_power_off(pcie->phy);
|
||||
err_exit_phy:
|
||||
if (pcie->phy)
|
||||
phy_exit(pcie->phy);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(iproc_pcie_setup);
|
||||
|
||||
int iproc_pcie_remove(struct iproc_pcie *pcie)
|
||||
{
|
||||
pci_stop_root_bus(pcie->root_bus);
|
||||
pci_remove_root_bus(pcie->root_bus);
|
||||
|
||||
if (pcie->phy) {
|
||||
phy_power_off(pcie->phy);
|
||||
phy_exit(pcie->phy);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(iproc_pcie_remove);
|
||||
|
||||
MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
|
||||
MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
42
drivers/pci/host/pcie-iproc.h
Normal file
42
drivers/pci/host/pcie-iproc.h
Normal file
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2015 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _PCIE_IPROC_H
|
||||
#define _PCIE_IPROC_H
|
||||
|
||||
#define IPROC_PCIE_MAX_NUM_IRQS 6
|
||||
|
||||
/**
|
||||
* iProc PCIe device
|
||||
* @dev: pointer to device data structure
|
||||
* @base: PCIe host controller I/O register base
|
||||
* @resources: linked list of all PCI resources
|
||||
* @sysdata: Per PCI controller data
|
||||
* @root_bus: pointer to root bus
|
||||
* @phy: optional PHY device that controls the Serdes
|
||||
* @irqs: interrupt IDs
|
||||
*/
|
||||
struct iproc_pcie {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
struct list_head *resources;
|
||||
struct pci_sys_data sysdata;
|
||||
struct pci_bus *root_bus;
|
||||
struct phy *phy;
|
||||
int irqs[IPROC_PCIE_MAX_NUM_IRQS];
|
||||
};
|
||||
|
||||
int iproc_pcie_setup(struct iproc_pcie *pcie);
|
||||
int iproc_pcie_remove(struct iproc_pcie *pcie);
|
||||
|
||||
#endif /* _PCIE_IPROC_H */
|
||||
@ -64,8 +64,8 @@
|
||||
#define LAR_ENABLE (1 << 1)
|
||||
|
||||
/* PCIe address reg & mask */
|
||||
#define PCIEPARL(x) (0x03400 + ((x) * 0x20))
|
||||
#define PCIEPARH(x) (0x03404 + ((x) * 0x20))
|
||||
#define PCIEPALR(x) (0x03400 + ((x) * 0x20))
|
||||
#define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
|
||||
#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
|
||||
#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
|
||||
#define PAR_ENABLE (1 << 31)
|
||||
@ -341,8 +341,9 @@ static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
|
||||
else
|
||||
res_start = res->start;
|
||||
|
||||
rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPARH(win));
|
||||
rcar_pci_write_reg(pcie, lower_32_bits(res_start), PCIEPARL(win));
|
||||
rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
|
||||
rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
|
||||
PCIEPALR(win));
|
||||
|
||||
/* First resource is for IO */
|
||||
mask = PAR_ENABLE;
|
||||
@ -501,7 +502,7 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
|
||||
|
||||
/* Enable MSI */
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI))
|
||||
rcar_pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
|
||||
rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
|
||||
|
||||
/* Finish initialization - establish a PCI Express link */
|
||||
rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
|
||||
|
||||
@ -738,7 +738,7 @@ static void ibm_unconfigure_device(struct pci_func *func)
|
||||
*/
|
||||
static u8 bus_structure_fixup(u8 busno)
|
||||
{
|
||||
struct pci_bus *bus;
|
||||
struct pci_bus *bus, *b;
|
||||
struct pci_dev *dev;
|
||||
u16 l;
|
||||
|
||||
@ -765,7 +765,11 @@ static u8 bus_structure_fixup(u8 busno)
|
||||
(l != 0x0000) && (l != 0xffff)) {
|
||||
debug("%s - Inside bus_structure_fixup()\n",
|
||||
__func__);
|
||||
pci_scan_bus(busno, ibmphp_pci_bus->ops, NULL);
|
||||
b = pci_scan_bus(busno, ibmphp_pci_bus->ops, NULL);
|
||||
if (!b)
|
||||
continue;
|
||||
|
||||
pci_bus_add_devices(b);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -18,6 +18,15 @@
|
||||
#include <linux/pm_qos.h>
|
||||
#include "pci.h"
|
||||
|
||||
/*
|
||||
* The UUID is defined in the PCI Firmware Specification available here:
|
||||
* https://www.pcisig.com/members/downloads/pcifw_r3_1_13Dec10.pdf
|
||||
*/
|
||||
const u8 pci_acpi_dsm_uuid[] = {
|
||||
0xd0, 0x37, 0xc9, 0xe5, 0x53, 0x35, 0x7a, 0x4d,
|
||||
0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
|
||||
};
|
||||
|
||||
phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
|
||||
{
|
||||
acpi_status status = AE_NOT_EXIST;
|
||||
@ -531,11 +540,32 @@ static struct pci_platform_pm_ops acpi_pci_platform_pm = {
|
||||
|
||||
void acpi_pci_add_bus(struct pci_bus *bus)
|
||||
{
|
||||
union acpi_object *obj;
|
||||
struct pci_host_bridge *bridge;
|
||||
|
||||
if (acpi_pci_disabled || !bus->bridge)
|
||||
return;
|
||||
|
||||
acpi_pci_slot_enumerate(bus);
|
||||
acpiphp_enumerate_slots(bus);
|
||||
|
||||
/*
|
||||
* For a host bridge, check its _DSM for function 8 and if
|
||||
* that is available, mark it in pci_host_bridge.
|
||||
*/
|
||||
if (!pci_is_root_bus(bus))
|
||||
return;
|
||||
|
||||
obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), pci_acpi_dsm_uuid, 3,
|
||||
RESET_DELAY_DSM, NULL);
|
||||
if (!obj)
|
||||
return;
|
||||
|
||||
if (obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 1) {
|
||||
bridge = pci_find_host_bridge(bus);
|
||||
bridge->ignore_reset_delay = 1;
|
||||
}
|
||||
ACPI_FREE(obj);
|
||||
}
|
||||
|
||||
void acpi_pci_remove_bus(struct pci_bus *bus)
|
||||
@ -561,6 +591,57 @@ static struct acpi_device *acpi_pci_find_companion(struct device *dev)
|
||||
check_children);
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_acpi_optimize_delay - optimize PCI D3 and D3cold delay from ACPI
|
||||
* @pdev: the PCI device whose delay is to be updated
|
||||
* @adev: the companion ACPI device of this PCI device
|
||||
*
|
||||
* Update the d3_delay and d3cold_delay of a PCI device from the ACPI _DSM
|
||||
* control method of either the device itself or the PCI host bridge.
|
||||
*
|
||||
* Function 8, "Reset Delay," applies to the entire hierarchy below a PCI
|
||||
* host bridge. If it returns one, the OS may assume that all devices in
|
||||
* the hierarchy have already completed power-on reset delays.
|
||||
*
|
||||
* Function 9, "Device Readiness Durations," applies only to the object
|
||||
* where it is located. It returns delay durations required after various
|
||||
* events if the device requires less time than the spec requires. Delays
|
||||
* from this function take precedence over the Reset Delay function.
|
||||
*
|
||||
* These _DSM functions are defined by the draft ECN of January 28, 2014,
|
||||
* titled "ACPI additions for FW latency optimizations."
|
||||
*/
|
||||
static void pci_acpi_optimize_delay(struct pci_dev *pdev,
|
||||
acpi_handle handle)
|
||||
{
|
||||
struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
|
||||
int value;
|
||||
union acpi_object *obj, *elements;
|
||||
|
||||
if (bridge->ignore_reset_delay)
|
||||
pdev->d3cold_delay = 0;
|
||||
|
||||
obj = acpi_evaluate_dsm(handle, pci_acpi_dsm_uuid, 3,
|
||||
FUNCTION_DELAY_DSM, NULL);
|
||||
if (!obj)
|
||||
return;
|
||||
|
||||
if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 5) {
|
||||
elements = obj->package.elements;
|
||||
if (elements[0].type == ACPI_TYPE_INTEGER) {
|
||||
value = (int)elements[0].integer.value / 1000;
|
||||
if (value < PCI_PM_D3COLD_WAIT)
|
||||
pdev->d3cold_delay = value;
|
||||
}
|
||||
if (elements[3].type == ACPI_TYPE_INTEGER) {
|
||||
value = (int)elements[3].integer.value / 1000;
|
||||
if (value < PCI_PM_D3_WAIT)
|
||||
pdev->d3_delay = value;
|
||||
}
|
||||
}
|
||||
ACPI_FREE(obj);
|
||||
}
|
||||
|
||||
static void pci_acpi_setup(struct device *dev)
|
||||
{
|
||||
struct pci_dev *pci_dev = to_pci_dev(dev);
|
||||
@ -569,6 +650,8 @@ static void pci_acpi_setup(struct device *dev)
|
||||
if (!adev)
|
||||
return;
|
||||
|
||||
pci_acpi_optimize_delay(pci_dev, adev->handle);
|
||||
|
||||
pci_acpi_add_pm_notifier(adev, pci_dev);
|
||||
if (!adev->wakeup.flags.valid)
|
||||
return;
|
||||
|
||||
@ -31,8 +31,6 @@
|
||||
#include <linux/pci-acpi.h>
|
||||
#include "pci.h"
|
||||
|
||||
#define DEVICE_LABEL_DSM 0x07
|
||||
|
||||
#ifdef CONFIG_DMI
|
||||
enum smbios_attr_enum {
|
||||
SMBIOS_ATTR_NONE = 0,
|
||||
@ -148,11 +146,6 @@ static inline void pci_remove_smbiosname_file(struct pci_dev *pdev)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
static const char device_label_dsm_uuid[] = {
|
||||
0xD0, 0x37, 0xC9, 0xE5, 0x53, 0x35, 0x7A, 0x4D,
|
||||
0x91, 0x17, 0xEA, 0x4D, 0x19, 0xC3, 0x43, 0x4D
|
||||
};
|
||||
|
||||
enum acpi_attr_enum {
|
||||
ACPI_ATTR_LABEL_SHOW,
|
||||
ACPI_ATTR_INDEX_SHOW,
|
||||
@ -179,7 +172,7 @@ static int dsm_get_label(struct device *dev, char *buf,
|
||||
if (!handle)
|
||||
return -1;
|
||||
|
||||
obj = acpi_evaluate_dsm(handle, device_label_dsm_uuid, 0x2,
|
||||
obj = acpi_evaluate_dsm(handle, pci_acpi_dsm_uuid, 0x2,
|
||||
DEVICE_LABEL_DSM, NULL);
|
||||
if (!obj)
|
||||
return -1;
|
||||
@ -219,7 +212,7 @@ static bool device_has_dsm(struct device *dev)
|
||||
if (!handle)
|
||||
return false;
|
||||
|
||||
return !!acpi_check_dsm(handle, device_label_dsm_uuid, 0x2,
|
||||
return !!acpi_check_dsm(handle, pci_acpi_dsm_uuid, 0x2,
|
||||
1 << DEVICE_LABEL_DSM);
|
||||
}
|
||||
|
||||
|
||||
@ -126,15 +126,16 @@ EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
|
||||
#ifdef CONFIG_HAS_IOMEM
|
||||
void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
|
||||
{
|
||||
struct resource *res = &pdev->resource[bar];
|
||||
|
||||
/*
|
||||
* Make sure the BAR is actually a memory resource, not an IO resource
|
||||
*/
|
||||
if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
|
||||
WARN_ON(1);
|
||||
if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
|
||||
dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
|
||||
return NULL;
|
||||
}
|
||||
return ioremap_nocache(pci_resource_start(pdev, bar),
|
||||
pci_resource_len(pdev, bar));
|
||||
return ioremap_nocache(res->start, resource_size(res));
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_ioremap_bar);
|
||||
#endif
|
||||
@ -145,19 +146,22 @@ static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
|
||||
u8 pos, int cap, int *ttl)
|
||||
{
|
||||
u8 id;
|
||||
u16 ent;
|
||||
|
||||
pci_bus_read_config_byte(bus, devfn, pos, &pos);
|
||||
|
||||
while ((*ttl)--) {
|
||||
pci_bus_read_config_byte(bus, devfn, pos, &pos);
|
||||
if (pos < 0x40)
|
||||
break;
|
||||
pos &= ~3;
|
||||
pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
|
||||
&id);
|
||||
pci_bus_read_config_word(bus, devfn, pos, &ent);
|
||||
|
||||
id = ent & 0xff;
|
||||
if (id == 0xff)
|
||||
break;
|
||||
if (id == cap)
|
||||
return pos;
|
||||
pos += PCI_CAP_LIST_NEXT;
|
||||
pos = (ent >> 8);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -2492,6 +2496,7 @@ u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
|
||||
*pinp = pin;
|
||||
return PCI_SLOT(dev->devfn);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_common_swizzle);
|
||||
|
||||
/**
|
||||
* pci_release_region - Release a PCI bar
|
||||
|
||||
@ -321,4 +321,6 @@ static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
|
||||
}
|
||||
#endif
|
||||
|
||||
struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
|
||||
|
||||
#endif /* DRIVERS_PCI_H */
|
||||
|
||||
@ -782,24 +782,6 @@ void pci_disable_link_state(struct pci_dev *pdev, int state)
|
||||
}
|
||||
EXPORT_SYMBOL(pci_disable_link_state);
|
||||
|
||||
void pcie_clear_aspm(struct pci_bus *bus)
|
||||
{
|
||||
struct pci_dev *child;
|
||||
|
||||
if (aspm_force)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Clear any ASPM setup that the firmware has carried out on this bus
|
||||
*/
|
||||
list_for_each_entry(child, &bus->devices, bus_list) {
|
||||
__pci_disable_link_state(child, PCIE_LINK_STATE_L0S |
|
||||
PCIE_LINK_STATE_L1 |
|
||||
PCIE_LINK_STATE_CLKPM,
|
||||
false, true);
|
||||
}
|
||||
}
|
||||
|
||||
static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
|
||||
{
|
||||
int i;
|
||||
|
||||
@ -6,6 +6,7 @@
|
||||
#include <linux/delay.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/pci_hotplug.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/module.h>
|
||||
@ -1520,6 +1521,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
|
||||
dev->dev.dma_mask = &dev->dma_mask;
|
||||
dev->dev.dma_parms = &dev->dma_parms;
|
||||
dev->dev.coherent_dma_mask = 0xffffffffull;
|
||||
of_pci_dma_configure(dev);
|
||||
|
||||
pci_set_dma_max_seg_size(dev, 65536);
|
||||
pci_set_dma_seg_boundary(dev, 0xffffffff);
|
||||
@ -1993,6 +1995,7 @@ err_out:
|
||||
kfree(b);
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_create_root_bus);
|
||||
|
||||
int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
|
||||
{
|
||||
@ -2087,7 +2090,6 @@ struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
|
||||
if (!found)
|
||||
pci_bus_update_busn_res_end(b, max);
|
||||
|
||||
pci_bus_add_devices(b);
|
||||
return b;
|
||||
}
|
||||
EXPORT_SYMBOL(pci_scan_root_bus);
|
||||
@ -2123,7 +2125,6 @@ struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
|
||||
b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
|
||||
if (b) {
|
||||
pci_scan_child_bus(b);
|
||||
pci_bus_add_devices(b);
|
||||
} else {
|
||||
pci_free_resource_list(&resources);
|
||||
}
|
||||
|
||||
@ -3182,7 +3182,7 @@ static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
|
||||
|| nhi->subsystem_vendor != 0x2222
|
||||
|| nhi->subsystem_device != 0x1111)
|
||||
goto out;
|
||||
dev_info(&dev->dev, "quirk: wating for thunderbolt to reestablish pci tunnels...\n");
|
||||
dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
|
||||
device_pm_wait_for_dev(&dev->dev, &nhi->dev);
|
||||
out:
|
||||
pci_dev_put(nhi);
|
||||
@ -3822,6 +3822,38 @@ static const struct pci_dev_acs_enabled {
|
||||
{ PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
|
||||
/* 82580 */
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
|
||||
/* 82576 */
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
|
||||
/* 82575 */
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
|
||||
/* I350 */
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
|
||||
/* 82571 (Quads omitted due to non-ACS switch) */
|
||||
{ PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
|
||||
/* Intel PCH root ports */
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
|
||||
{ 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
|
||||
{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
|
||||
|
||||
@ -139,6 +139,7 @@ void pci_stop_root_bus(struct pci_bus *bus)
|
||||
/* stop the host bridge */
|
||||
device_release_driver(&host_bridge->dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_stop_root_bus);
|
||||
|
||||
void pci_remove_root_bus(struct pci_bus *bus)
|
||||
{
|
||||
@ -158,3 +159,4 @@ void pci_remove_root_bus(struct pci_bus *bus)
|
||||
/* remove the host bridge */
|
||||
device_unregister(&host_bridge->dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_remove_root_bus);
|
||||
|
||||
@ -1750,3 +1750,4 @@ void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
|
||||
__pci_bus_assign_resources(bus, &add_list, NULL);
|
||||
BUG_ON(!list_empty(&add_list));
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);
|
||||
|
||||
@ -65,3 +65,4 @@ void pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *),
|
||||
for_each_pci_dev(dev)
|
||||
pdev_fixup_irq(dev, swizzle, map_irq);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_fixup_irqs);
|
||||
|
||||
@ -120,6 +120,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource)
|
||||
if (!root) {
|
||||
dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
|
||||
resource, res);
|
||||
res->flags |= IORESOURCE_UNSET;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@ -127,6 +128,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource)
|
||||
if (conflict) {
|
||||
dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
|
||||
resource, res, conflict->name, conflict);
|
||||
res->flags |= IORESOURCE_UNSET;
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
|
||||
@ -246,13 +246,16 @@ static void quirk_system_pci_resources(struct pnp_dev *dev)
|
||||
*/
|
||||
for_each_pci_dev(pdev) {
|
||||
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
|
||||
unsigned long type;
|
||||
unsigned long flags, type;
|
||||
|
||||
type = pci_resource_flags(pdev, i) &
|
||||
(IORESOURCE_IO | IORESOURCE_MEM);
|
||||
flags = pci_resource_flags(pdev, i);
|
||||
type = flags & (IORESOURCE_IO | IORESOURCE_MEM);
|
||||
if (!type || pci_resource_len(pdev, i) == 0)
|
||||
continue;
|
||||
|
||||
if (flags & IORESOURCE_UNSET)
|
||||
continue;
|
||||
|
||||
pci_start = pci_resource_start(pdev, i);
|
||||
pci_end = pci_resource_end(pdev, i);
|
||||
for (j = 0;
|
||||
|
||||
@ -53,6 +53,7 @@ static inline struct device_node *of_cpu_device_node_get(int cpu)
|
||||
return of_node_get(cpu_dev->of_node);
|
||||
}
|
||||
|
||||
void of_dma_configure(struct device *dev, struct device_node *np);
|
||||
#else /* CONFIG_OF */
|
||||
|
||||
static inline int of_driver_match_device(struct device *dev,
|
||||
@ -90,6 +91,8 @@ static inline struct device_node *of_cpu_device_node_get(int cpu)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
static inline void of_dma_configure(struct device *dev, struct device_node *np)
|
||||
{}
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
#endif /* _LINUX_OF_DEVICE_H */
|
||||
|
||||
@ -12,7 +12,8 @@ extern int of_get_dma_window(struct device_node *dn, const char *prefix,
|
||||
size_t *size);
|
||||
|
||||
extern void of_iommu_init(void);
|
||||
extern struct iommu_ops *of_iommu_configure(struct device *dev);
|
||||
extern struct iommu_ops *of_iommu_configure(struct device *dev,
|
||||
struct device_node *master_np);
|
||||
|
||||
#else
|
||||
|
||||
@ -24,7 +25,8 @@ static inline int of_get_dma_window(struct device_node *dn, const char *prefix,
|
||||
}
|
||||
|
||||
static inline void of_iommu_init(void) { }
|
||||
static inline struct iommu_ops *of_iommu_configure(struct device *dev)
|
||||
static inline struct iommu_ops *of_iommu_configure(struct device *dev,
|
||||
struct device_node *master_np)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@ -16,6 +16,7 @@ int of_pci_get_devfn(struct device_node *np);
|
||||
int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin);
|
||||
int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
|
||||
int of_get_pci_domain_nr(struct device_node *node);
|
||||
void of_pci_dma_configure(struct pci_dev *pci_dev);
|
||||
#else
|
||||
static inline int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq)
|
||||
{
|
||||
@ -50,6 +51,8 @@ of_get_pci_domain_nr(struct device_node *node)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
static inline void of_pci_dma_configure(struct pci_dev *pci_dev) { }
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_ADDRESS)
|
||||
|
||||
@ -77,6 +77,11 @@ static inline void acpiphp_remove_slots(struct pci_bus *bus) { }
|
||||
static inline void acpiphp_check_host_bridge(struct acpi_device *adev) { }
|
||||
#endif
|
||||
|
||||
extern const u8 pci_acpi_dsm_uuid[];
|
||||
#define DEVICE_LABEL_DSM 0x07
|
||||
#define RESET_DELAY_DSM 0x08
|
||||
#define FUNCTION_DELAY_DSM 0x09
|
||||
|
||||
#else /* CONFIG_ACPI */
|
||||
static inline void acpi_pci_add_bus(struct pci_bus *bus) { }
|
||||
static inline void acpi_pci_remove_bus(struct pci_bus *bus) { }
|
||||
|
||||
@ -29,7 +29,6 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev);
|
||||
void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
|
||||
void pci_disable_link_state(struct pci_dev *pdev, int state);
|
||||
void pci_disable_link_state_locked(struct pci_dev *pdev, int state);
|
||||
void pcie_clear_aspm(struct pci_bus *bus);
|
||||
void pcie_no_aspm(void);
|
||||
#else
|
||||
static inline void pcie_aspm_init_link_state(struct pci_dev *pdev)
|
||||
@ -47,9 +46,6 @@ static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
|
||||
static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
|
||||
{
|
||||
}
|
||||
static inline void pcie_clear_aspm(struct pci_bus *bus)
|
||||
{
|
||||
}
|
||||
static inline void pcie_no_aspm(void)
|
||||
{
|
||||
}
|
||||
|
||||
@ -406,6 +406,7 @@ struct pci_host_bridge {
|
||||
struct list_head windows; /* resource_entry */
|
||||
void (*release_fn)(struct pci_host_bridge *);
|
||||
void *release_data;
|
||||
unsigned int ignore_reset_delay:1; /* for entire hierarchy */
|
||||
};
|
||||
|
||||
#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
|
||||
@ -510,6 +511,9 @@ static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
|
||||
return dev->bus->self;
|
||||
}
|
||||
|
||||
struct device *pci_get_host_bridge_device(struct pci_dev *dev);
|
||||
void pci_put_host_bridge_device(struct device *dev);
|
||||
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user