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phy: qcom-qmp-ufs: rework regs layout arrays

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Use symbolic names for the values inside reg layout arrays. New register
names are added following the PCS register layout that is used by the
particular PHY.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221110192248.873973-8-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Dmitry Baryshkov 2022-11-10 22:22:42 +03:00 committed by Vinod Koul
parent cbd06cdedf
commit 3b4bf465dd
3 changed files with 17 additions and 9 deletions
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5
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h
View File

@ -6,6 +6,9 @@
#ifndef QCOM_PHY_QMP_PCS_UFS_V2_H_
#define QCOM_PHY_QMP_PCS_UFS_V2_H_
#define QPHY_V2_PCS_UFS_PHY_START 0x000
#define QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL 0x004
#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x034
#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL 0x038
#define QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03c
@ -17,4 +20,6 @@
#define QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2 0x148
#define QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND 0x154
#define QPHY_V2_PCS_UFS_READY_STATUS 0x168
#endif

3
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h
View File

@ -6,12 +6,15 @@
#ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_
#define QCOM_PHY_QMP_PCS_UFS_V3_H_
#define QPHY_V3_PCS_UFS_PHY_START 0x000
#define QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL 0x004
#define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c
#define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034
#define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134
#define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138
#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c
#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140
#define QPHY_V3_PCS_UFS_READY_STATUS 0x160
#define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc
#define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1 0x1c4

18
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
View File

@ -70,21 +70,21 @@ enum qphy_reg_layout {
};
static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = 0x00,
[QPHY_PCS_READY_STATUS] = 0x168,
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
[QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START,
[QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
};
static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = 0x00,
[QPHY_PCS_READY_STATUS] = 0x160,
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
[QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START,
[QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL,
};
static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = 0x00,
[QPHY_PCS_READY_STATUS] = 0x168,
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
[QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START,
[QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
};
static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {