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serial: sh-sci: Add support for RZ/G2L SoC

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Add serial support for RZ/G2L SoC with earlycon and
extended mode register support.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210603221758.10305-11-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Biju Das 2021-06-03 23:17:56 +01:00 committed by Greg Kroah-Hartman
parent d157fca711
commit 3b2cd60689
2 changed files with 12 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/tty/serial/sh-sci.c
View File

@ -289,7 +289,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
}, },
/* /*
* The "SCIFA" that is in RZ/T and RZ/A2. * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
* It looks like a normal SCIF with FIFO data, but with a * It looks like a normal SCIF with FIFO data, but with a
* compressed address space. Also, the break out of interrupts * compressed address space. Also, the break out of interrupts
* are different: ERI/BRI, RXI, TXI, TEI, DRI. * are different: ERI/BRI, RXI, TXI, TEI, DRI.
@ -306,6 +306,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
[SCFDR] = { 0x0E, 16 }, [SCFDR] = { 0x0E, 16 },
[SCSPTR] = { 0x10, 16 }, [SCSPTR] = { 0x10, 16 },
[SCLSR] = { 0x12, 16 }, [SCLSR] = { 0x12, 16 },
[SEMR] = { 0x14, 8 },
}, },
.fifosize = 16, .fifosize = 16,
.overrun_reg = SCLSR, .overrun_reg = SCLSR,
@ -2514,6 +2515,9 @@ done:
if (termios->c_cflag & PARENB) if (termios->c_cflag & PARENB)
bits++; bits++;
if (sci_getreg(port, SEMR)->size)
serial_port_out(port, SEMR, 0);
if (best_clk >= 0) { if (best_clk >= 0) {
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
switch (srr + 1) { switch (srr + 1) {
@ -3170,6 +3174,10 @@ static const struct of_device_id of_sci_match[] = {
.compatible = "renesas,scif-r7s9210", .compatible = "renesas,scif-r7s9210",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
}, },
{
.compatible = "renesas,scif-r9a07g044",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
},
/* Family-specific types */ /* Family-specific types */
{ {
.compatible = "renesas,rcar-gen1-scif", .compatible = "renesas,rcar-gen1-scif",
@ -3452,6 +3460,7 @@ static int __init rzscifa_early_console_setup(struct earlycon_device *device,
port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
return early_console_setup(device, PORT_SCIF); return early_console_setup(device, PORT_SCIF);
} }
static int __init scifa_early_console_setup(struct earlycon_device *device, static int __init scifa_early_console_setup(struct earlycon_device *device,
const char *opt) const char *opt)
{ {
@ -3471,6 +3480,7 @@ static int __init hscif_early_console_setup(struct earlycon_device *device,
OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);

1
drivers/tty/serial/sh-sci.h
View File

@ -31,6 +31,7 @@ enum {
SCCKS, /* BRG Clock Select Register */ SCCKS, /* BRG Clock Select Register */
HSRTRGR, /* Rx FIFO Data Count Trigger Register */ HSRTRGR, /* Rx FIFO Data Count Trigger Register */
HSTTRGR, /* Tx FIFO Data Count Trigger Register */ HSTTRGR, /* Tx FIFO Data Count Trigger Register */
SEMR, /* Serial extended mode register */
SCIx_NR_REGS, SCIx_NR_REGS,
}; };