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RDMA/hns: Replace tab with space in the right-side comments

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There should be a space between the code and the comment on the right.

Link: https://lore.kernel.org/r/20211119140208.40416-4-liangwenpeng@huawei.com
Signed-off-by: Xinhao Liu <liuxinhao5@hisilicon.com>
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Xinhao Liu 2021-11-19 22:02:02 +08:00 committed by Jason Gunthorpe
parent ea393549a3
commit 3aecfc3802
3 changed files with 15 additions and 15 deletions
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26
drivers/infiniband/hw/hns/hns_roce_device.h
View File

@ -354,10 +354,10 @@ struct hns_roce_mr {
u64 size; /* Address range of MR */
u32 key; /* Key of MR */
u32 pd; /* PD num of MR */
u32 access; /* Access permission of MR */
u32 access; /* Access permission of MR */
int enabled; /* MR's active status */
int type; /* MR's register type */
u32 pbl_hop_num; /* multi-hop number */
int type; /* MR's register type */
u32 pbl_hop_num; /* multi-hop number */
struct hns_roce_mtr pbl_mtr;
u32 npages;
dma_addr_t *page_list;
@ -375,16 +375,16 @@ struct hns_roce_wq {
u32 max_gs;
u32 rsv_sge;
int offset;
int wqe_shift; /* WQE size */
int wqe_shift; /* WQE size */
u32 head;
u32 tail;
void __iomem *db_reg;
};
struct hns_roce_sge {
unsigned int sge_cnt; /* SGE num */
unsigned int sge_cnt; /* SGE num */
int offset;
int sge_shift; /* SGE size */
int sge_shift; /* SGE size */
};
struct hns_roce_buf_list {
@ -672,9 +672,9 @@ struct hns_roce_qp {
unsigned long flush_flag;
struct hns_roce_work flush_work;
struct hns_roce_rinl_buf rq_inl_buf;
struct list_head node; /* all qps are on a list */
struct list_head rq_node; /* all recv qps are on a list */
struct list_head sq_node; /* all send qps are on a list */
struct list_head node; /* all qps are on a list */
struct list_head rq_node; /* all recv qps are on a list */
struct list_head sq_node; /* all send qps are on a list */
};
struct hns_roce_ib_iboe {
@ -855,7 +855,7 @@ struct hns_roce_caps {
u32 cqc_timer_ba_pg_sz;
u32 cqc_timer_buf_pg_sz;
u32 cqc_timer_hop_num;
u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */
u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */
u32 cqe_buf_pg_sz;
u32 cqe_hop_num;
u32 srqwqe_ba_pg_sz;
@ -874,7 +874,7 @@ struct hns_roce_caps {
u32 gmv_hop_num;
u32 sl_num;
u32 llm_buf_pg_sz;
u32 chunk_sz; /* chunk size in non multihop mode */
u32 chunk_sz; /* chunk size in non multihop mode */
u64 flags;
u16 default_ceq_max_cnt;
u16 default_ceq_period;
@ -1001,8 +1001,8 @@ struct hns_roce_dev {
int loop_idc;
u32 sdb_offset;
u32 odb_offset;
dma_addr_t tptr_dma_addr; /* only for hw v1 */
u32 tptr_size; /* only for hw v1 */
dma_addr_t tptr_dma_addr; /* only for hw v1 */
u32 tptr_size; /* only for hw v1 */
const struct hns_roce_hw *hw;
void *priv;
struct workqueue_struct *irq_workq;

2
drivers/infiniband/hw/hns/hns_roce_hw_v2.h
View File

@ -1441,7 +1441,7 @@ struct hns_roce_v2_priv {
struct hns_roce_dip {
u8 dgid[GID_LEN_V2];
u32 dip_idx;
struct list_head node; /* all dips are on a list */
struct list_head node; /* all dips are on a list */
};
#define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0

2
drivers/infiniband/hw/hns/hns_roce_mr.c
View File

@ -81,7 +81,7 @@ static int alloc_mr_key(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr)
return -ENOMEM;
}
mr->key = hw_index_to_key(id); /* MR key */
mr->key = hw_index_to_key(id); /* MR key */
err = hns_roce_table_get(hr_dev, &hr_dev->mr_table.mtpt_table,
(unsigned long)id);