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This is the second batch of clk driver updates that needed

Browse Source 
a little more time to soak in linux-next.
 
  - Use modern i2c probe in vc5
  - Cleanup some includes
  - Update links to datasheets
  - Add UniPhier NX1 SoC clk support
  - Fix DT bindings for SiFive FU740
  - Revert the module platform driver support for Rockchip out
    because it wasn't actually tested
  - Fix the composite clk code again as the previous fix had a
    one line bug that broke rate changes for clks that want to use
    the same parent still
  - Use the right table for a divider in ast2600 driver
  - Get rid of gcc_aggre1_pnoc_ahb_clk in qcom clk driver again because
    its critical but unused
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmGPWzIRHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSWQehAAlxoUxicL5OHtM5joKiCW5Tb+7faR/oie
 qBwQfwG6l72jtuAQc9hZFVz8ATozcvkoEf0u6Q+/y1wsAZtJud6zFPW6N7DJlB9B
 3XE1o98/rzKHFr9YoIDIJb6cG+LKzK3GovRbQtQi3exb0a80xtmeU0acu1zIJSyr
 L3tfoS44Om2a/SduWGfstOyj8klFPbh0lfypM6giLBkmEUsFTdGcSq47J5qgOl3h
 pJY3/oRqE075ylD9J30HwM0PhcDA9kKCz7yqPTf8cHPsHg/LbVSZ/BycQWdtvXhf
 GLAdndgN9DHi2gg41dq85iecpPJ8m5zZ0VwYV9KdquNyKVR89rTiJklmXYStE408
 uSzxod4vbbEfUqbBfNglbNghTCJTuwXoArFVrja70MImW2s6jrEeHnTH9bwLxVjm
 efZCrMgSuVdI/w1V0FP0lcyhd8xXq/9OfupbbLVc79RoacK6xKEb8o5BByVjQg1g
 3PvKiDAUDS6OzJKtvgHfaJ4cFgSHlzmYxfhOmDOODaj83URvz+1faUoXU4BQlVeB
 JUEF1O3duR0X9lDx28MhEdl4ROBhFVA5sBgBvtOn9GbiOopaeq5k2Q2nbOMB1cKR
 8+SpPFMQuI/L5QKhsg5q0GlpfFaFc3Ax2Y0b5UxHWzhuGGJOpi7Kt5sIj6OIQA8s
 oW3ugMiY8TA=
 =j1rC
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull more clk updates from Stephen Boyd:
 "This is the second batch of clk driver updates that needed a little
  more time to soak in linux-next.

   - Use modern i2c probe in vc5

   - Cleanup some includes

   - Update links to datasheets

   - Add UniPhier NX1 SoC clk support

   - Fix DT bindings for SiFive FU740

   - Revert the module platform driver support for Rockchip because it
     wasn't actually tested

   - Fix the composite clk code again as the previous fix had a one line
     bug that broke rate changes for clks that want to use the same
     parent still

   - Use the right table for a divider in ast2600 driver

   - Get rid of gcc_aggre1_pnoc_ahb_clk in qcom clk driver again because
     its critical but unused"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clk
  clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular composites
  clk/ast2600: Fix soc revision for AHB
  clk: composite: Fix 'switching' to same clock
  clk: rockchip: drop module parts from rk3399 and rk3568 drivers
  Revert "clk: rockchip: use module_platform_driver_probe"
  clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.c
  dt-bindings: clock: fu740-prci: add reset-cells
  clk: uniphier: Add SoC-glue clock source selector support for Pro4
  dt-bindings: clock: uniphier: Add clock binding for SoC-glue
  clk: uniphier: Add NX1 clock support
  dt-bindings: clock: uniphier: Add NX1 clock binding
  clk: uniphier: Add audio system and video input clock control for PXs3
  clk: si5351: Update datasheet references
  clk: vc5: Use i2c .probe_new
  clk/actions/owl-factor.c: remove superfluous headers
  clk: ingenic: Fix bugs with divided dividers
This commit is contained in:
Linus Torvalds 2021-11-13 13:07:29 -08:00
commit 3ad7befd48
19 changed files with 105 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/clock/sifive/fu740-prci.yaml
View File

@ -42,6 +42,9 @@ properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
@ -57,4 +60,5 @@ examples:
reg = <0x10000000 0x1000>;
clocks = <&hfclk>, <&rtcclk>;
#clock-cells = <1>;
#reset-cells = <1>;
};

2
Documentation/devicetree/bindings/clock/silabs,si5351.txt
View File

@ -2,7 +2,7 @@ Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
Reference
[1] Si5351A/B/C Data Sheet
https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
The Si5351a/b/c are programmable i2c clock generators with up to 8 output
clocks. Si5351a also has a reduced pin-count package (MSOP10) where only

6
Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml
View File

@ -23,6 +23,7 @@ properties:
- socionext,uniphier-ld11-clock
- socionext,uniphier-ld20-clock
- socionext,uniphier-pxs3-clock
- socionext,uniphier-nx1-clock
- description: Media I/O (MIO) clock, SD clock
enum:
- socionext,uniphier-ld4-mio-clock
@ -33,6 +34,7 @@ properties:
- socionext,uniphier-ld11-mio-clock
- socionext,uniphier-ld20-sd-clock
- socionext,uniphier-pxs3-sd-clock
- socionext,uniphier-nx1-sd-clock
- description: Peripheral clock
enum:
- socionext,uniphier-ld4-peri-clock
@ -43,6 +45,10 @@ properties:
- socionext,uniphier-ld11-peri-clock
- socionext,uniphier-ld20-peri-clock
- socionext,uniphier-pxs3-peri-clock
- socionext,uniphier-nx1-peri-clock
- description: SoC-glue clock
enum:
- socionext,uniphier-pro4-sg-clock
"#clock-cells":
const: 1

1
drivers/clk/actions/owl-factor.c
View File

@ -10,7 +10,6 @@
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "owl-factor.h"

12
drivers/clk/clk-ast2600.c
View File

@ -51,6 +51,8 @@ static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
static struct clk_hw_onecell_data *aspeed_g6_clk_data;
static void __iomem *scu_g6_base;
/* AST2600 revision: A0, A1, A2, etc */
static u8 soc_rev;
/*
* Clocks marked with CLK_IS_CRITICAL:
@ -191,9 +193,8 @@ static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
{
unsigned int mult, div;
u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV);
if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) {
if (soc_rev >= 2) {
if (val & BIT(24)) {
/* Pass through mode */
mult = div = 1;
@ -707,7 +708,7 @@ static const u32 ast2600_a1_axi_ahb200_tbl[] = {
static void __init aspeed_g6_cc(struct regmap *map)
{
struct clk_hw *hw;
u32 val, div, divbits, chip_id, axi_div, ahb_div;
u32 val, div, divbits, axi_div, ahb_div;
clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
@ -738,8 +739,7 @@ static void __init aspeed_g6_cc(struct regmap *map)
axi_div = 2;
divbits = (val >> 11) & 0x3;
regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
if (chip_id & BIT(16)) {
if (soc_rev >= 1) {
if (!divbits) {
ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3];
if (val & BIT(16))
@ -784,6 +784,8 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
if (!scu_g6_base)
return;
soc_rev = (readl(scu_g6_base + ASPEED_G6_SILICON_REV) & CHIP_REVISION_ID) >> 16;
aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
ASPEED_G6_NUM_CLKS), GFP_KERNEL);
if (!aspeed_g6_clk_data)

1
drivers/clk/clk-composite.c
View File

@ -97,6 +97,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw,
return ret;
req->rate = tmp_req.rate;
req->best_parent_hw = tmp_req.best_parent_hw;
req->best_parent_rate = tmp_req.best_parent_rate;
return 0;

8
drivers/clk/clk-si5351.c
View File

@ -1,15 +1,15 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* clk-si5351.c: Silicon Laboratories Si5351A/B/C I2C Clock Generator
* clk-si5351.c: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* Rabeeh Khoury <rabeeh@solid-run.com>
*
* References:
* [1] "Si5351A/B/C Data Sheet"
* https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
* [2] "Manually Generating an Si5351 Register Map"
* https://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
* https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
* [2] "AN619: Manually Generating an Si5351 Register Map"
* https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN619.pdf
*/
#include <linux/module.h>

2
drivers/clk/clk-si5351.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* clk-si5351.h: Silicon Laboratories Si5351A/B/C I2C Clock Generator
* clk-si5351.h: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* Rabeeh Khoury <rabeeh@solid-run.com>

4
drivers/clk/clk-versaclock5.c
View File

@ -905,7 +905,7 @@ output_error:
static const struct of_device_id clk_vc5_of_match[];
static int vc5_probe(struct i2c_client *client, const struct i2c_device_id *id)
static int vc5_probe(struct i2c_client *client)
{
unsigned int oe, sd, src_mask = 0, src_val = 0;
struct vc5_driver_data *vc5;
@ -1244,7 +1244,7 @@ static struct i2c_driver vc5_driver = {
.pm = &vc5_pm_ops,
.of_match_table = clk_vc5_of_match,
},
.probe = vc5_probe,
.probe_new = vc5_probe,
.remove = vc5_remove,
.id_table = vc5_id,
};

4
drivers/clk/imx/clk.h
View File

@ -391,11 +391,11 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
#define imx8m_clk_hw_composite(name, parent_names, reg) \
_imx8m_clk_hw_composite(name, parent_names, reg, \
IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
#define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
_imx8m_clk_hw_composite(name, parent_names, reg, \
IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
#define imx8m_clk_hw_composite_bus(name, parent_names, reg) \
_imx8m_clk_hw_composite(name, parent_names, reg, \

6
drivers/clk/ingenic/cgu.c
View File

@ -453,15 +453,15 @@ ingenic_clk_calc_div(struct clk_hw *hw,
}
/* Impose hardware constraints */
div = min_t(unsigned, div, 1 << clk_info->div.bits);
div = max_t(unsigned, div, 1);
div = clamp_t(unsigned int, div, clk_info->div.div,
clk_info->div.div << clk_info->div.bits);
/*
* If the divider value itself must be divided before being written to
* the divider register, we must ensure we don't have any bits set that
* would be lost as a result of doing so.
*/
div /= clk_info->div.div;
div = DIV_ROUND_UP(div, clk_info->div.div);
div *= clk_info->div.div;
return div;

2
drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
View File

@ -10,8 +10,6 @@
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8195-clk.h>
static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
.set_ofs = 0xe08,
.clr_ofs = 0xe04,

15
drivers/clk/qcom/gcc-msm8996.c
View File

@ -2937,20 +2937,6 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
},
};
static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
.halt_reg = 0x82014,
.clkr = {
.enable_reg = 0x82014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre1_pnoc_ahb_clk",
.parent_names = (const char *[]){ "periph_noc_clk_src" },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre2_ufs_axi_clk = {
.halt_reg = 0x83014,
.clkr = {
@ -3474,7 +3460,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
[GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
[GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
[GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
[GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
[GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
[GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
[GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,

4
drivers/clk/rockchip/Kconfig
View File

@ -80,14 +80,14 @@ config CLK_RK3368
Build the driver for RK3368 Clock Driver.
config CLK_RK3399
tristate "Rockchip RK3399 clock controller support"
bool "Rockchip RK3399 clock controller support"
depends on ARM64 || COMPILE_TEST
default y
help
Build the driver for RK3399 Clock Driver.
config CLK_RK3568
tristate "Rockchip RK3568 clock controller support"
bool "Rockchip RK3568 clock controller support"
depends on ARM64 || COMPILE_TEST
default y
help

6
drivers/clk/rockchip/clk-rk3399.c
View File

@ -1630,7 +1630,6 @@ static const struct of_device_id clk_rk3399_match_table[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
static int __init clk_rk3399_probe(struct platform_device *pdev)
{
@ -1656,7 +1655,4 @@ static struct platform_driver clk_rk3399_driver = {
.suppress_bind_attrs = true,
},
};
module_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
MODULE_LICENSE("GPL");
builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);

6
drivers/clk/rockchip/clk-rk3568.c
View File

@ -1693,7 +1693,6 @@ static const struct of_device_id clk_rk3568_match_table[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, clk_rk3568_match_table);
static int __init clk_rk3568_probe(struct platform_device *pdev)
{
@ -1719,7 +1718,4 @@ static struct platform_driver clk_rk3568_driver = {
.suppress_bind_attrs = true,
},
};
module_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);
MODULE_DESCRIPTION("Rockchip RK3568 Clock Driver");
MODULE_LICENSE("GPL");
builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);

17
drivers/clk/uniphier/clk-uniphier-core.c
View File

@ -132,6 +132,10 @@ static const struct of_device_id uniphier_clk_match[] = {
.compatible = "socionext,uniphier-pxs3-clock",
.data = uniphier_pxs3_sys_clk_data,
},
{
.compatible = "socionext,uniphier-nx1-clock",
.data = uniphier_nx1_sys_clk_data,
},
/* Media I/O clock, SD clock */
{
.compatible = "socionext,uniphier-ld4-mio-clock",
@ -165,6 +169,10 @@ static const struct of_device_id uniphier_clk_match[] = {
.compatible = "socionext,uniphier-pxs3-sd-clock",
.data = uniphier_pro5_sd_clk_data,
},
{
.compatible = "socionext,uniphier-nx1-sd-clock",
.data = uniphier_pro5_sd_clk_data,
},
/* Peripheral clock */
{
.compatible = "socionext,uniphier-ld4-peri-clock",
@ -198,6 +206,15 @@ static const struct of_device_id uniphier_clk_match[] = {
.compatible = "socionext,uniphier-pxs3-peri-clock",
.data = uniphier_pro4_peri_clk_data,
},
{
.compatible = "socionext,uniphier-nx1-peri-clock",
.data = uniphier_pro4_peri_clk_data,
},
/* SoC-glue clock */
{
.compatible = "socionext,uniphier-pro4-sg-clock",
.data = uniphier_pro4_sg_clk_data,
},
{ /* sentinel */ }
};

47
drivers/clk/uniphier/clk-uniphier-sys.c
View File

@ -20,6 +20,10 @@
UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
#define UNIPHIER_NX1_SYS_CLK_SD \
UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
#define UNIPHIER_LD4_SYS_CLK_NAND(idx) \
UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
@ -288,6 +292,8 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
UNIPHIER_LD11_SYS_CLK_AIO(40),
UNIPHIER_LD11_SYS_CLK_EXIV(42),
/* CPU gears */
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
@ -300,3 +306,44 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
"spll/4", "spll/8", "s2pll/4", "s2pll/8"),
{ /* sentinel */ }
};
const struct uniphier_clk_data uniphier_nx1_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 100, 1), /* ARM: 2500 MHz */
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 32, 1), /* 800 MHz */
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 6),
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
UNIPHIER_NX1_SYS_CLK_SD,
UNIPHIER_CLK_GATE("emmc", 4, NULL, 0x2108, 8),
UNIPHIER_CLK_GATE("ether", 6, NULL, 0x210c, 0),
UNIPHIER_CLK_GATE("usb30-0", 12, NULL, 0x210c, 16), /* =GIO */
UNIPHIER_CLK_GATE("usb30-1", 13, NULL, 0x210c, 20), /* =GIO1P */
UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 24),
UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 25),
UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 26),
UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 8),
UNIPHIER_CLK_GATE("voc", 52, NULL, 0x2110, 0),
UNIPHIER_CLK_GATE("hdmitx", 58, NULL, 0x2110, 8),
/* CPU gears */
UNIPHIER_CLK_DIV5("cpll", 2, 4, 8, 16, 32),
UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 5,
"cpll/2", "cpll/4", "cpll/8", "cpll/16",
"cpll/32"),
{ /* sentinel */ }
};
const struct uniphier_clk_data uniphier_pro4_sg_clk_data[] = {
UNIPHIER_CLK_DIV("gpll", 4),
{
.name = "sata-ref",
.type = UNIPHIER_CLK_TYPE_MUX,
.idx = 0,
.data.mux = {
.parent_names = { "gpll/4", "ref", },
.num_parents = 2,
.reg = 0x1a28,
.masks = { 0x1, 0x1, },
.vals = { 0x0, 0x1, },
},
},
{ /* sentinel */ }
};

6
drivers/clk/uniphier/clk-uniphier.h
View File

@ -119,6 +119,10 @@ struct uniphier_clk_data {
UNIPHIER_CLK_DIV2(parent, div0, div1), \
UNIPHIER_CLK_DIV2(parent, div2, div3)
#define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \
UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3), \
UNIPHIER_CLK_DIV(parent, div4)
struct clk_hw *uniphier_clk_register_cpugear(struct device *dev,
struct regmap *regmap,
const char *name,
@ -146,9 +150,11 @@ extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_nx1_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_ld4_mio_clk_data[];
extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];
extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
extern const struct uniphier_clk_data uniphier_pro4_sg_clk_data[];
#endif /* __CLK_UNIPHIER_H__ */