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Merge branch 'tip/perf/core' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-2.6-trace into perf/core

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This commit is contained in:
Ingo Molnar 2010-09-15 10:27:31 +02:00
commit 3aabae7d9d
599 changed files with 6551 additions and 4419 deletions
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1
Documentation/DocBook/device-drivers.tmpl
View File

@ -46,7 +46,6 @@
<sect1><title>Atomic and pointer manipulation</title>
!Iarch/x86/include/asm/atomic.h
!Iarch/x86/include/asm/unaligned.h
</sect1>
<sect1><title>Delaying, scheduling, and timer routines</title>

1
Documentation/DocBook/kernel-api.tmpl
View File

@ -57,7 +57,6 @@
</para>
<sect1><title>String Conversions</title>
!Ilib/vsprintf.c
!Elib/vsprintf.c
</sect1>
<sect1><title>String Manipulation</title>

6
Documentation/DocBook/kernel-locking.tmpl
View File

@ -1961,6 +1961,12 @@ machines due to caching.
</sect1>
</chapter>
<chapter id="apiref">
<title>Mutex API reference</title>
!Iinclude/linux/mutex.h
!Ekernel/mutex.c
</chapter>
<chapter id="references">
<title>Further reading</title>

5
Documentation/DocBook/tracepoint.tmpl
View File

@ -104,4 +104,9 @@
<title>Block IO</title>
!Iinclude/trace/events/block.h
</chapter>
<chapter id="workqueue">
<title>Workqueue</title>
!Iinclude/trace/events/workqueue.h
</chapter>
</book>

45
Documentation/block/cfq-iosched.txt Normal file
View File

@ -0,0 +1,45 @@
CFQ ioscheduler tunables
========================
slice_idle
----------
This specifies how long CFQ should idle for next request on certain cfq queues
(for sequential workloads) and service trees (for random workloads) before
queue is expired and CFQ selects next queue to dispatch from.
By default slice_idle is a non-zero value. That means by default we idle on
queues/service trees. This can be very helpful on highly seeky media like
single spindle SATA/SAS disks where we can cut down on overall number of
seeks and see improved throughput.
Setting slice_idle to 0 will remove all the idling on queues/service tree
level and one should see an overall improved throughput on faster storage
devices like multiple SATA/SAS disks in hardware RAID configuration. The down
side is that isolation provided from WRITES also goes down and notion of
IO priority becomes weaker.
So depending on storage and workload, it might be useful to set slice_idle=0.
In general I think for SATA/SAS disks and software RAID of SATA/SAS disks
keeping slice_idle enabled should be useful. For any configurations where
there are multiple spindles behind single LUN (Host based hardware RAID
controller or for storage arrays), setting slice_idle=0 might end up in better
throughput and acceptable latencies.
CFQ IOPS Mode for group scheduling
===================================
Basic CFQ design is to provide priority based time slices. Higher priority
process gets bigger time slice and lower priority process gets smaller time
slice. Measuring time becomes harder if storage is fast and supports NCQ and
it would be better to dispatch multiple requests from multiple cfq queues in
request queue at a time. In such scenario, it is not possible to measure time
consumed by single queue accurately.
What is possible though is to measure number of requests dispatched from a
single queue and also allow dispatch from multiple cfq queue at the same time.
This effectively becomes the fairness in terms of IOPS (IO operations per
second).
If one sets slice_idle=0 and if storage supports NCQ, CFQ internally switches
to IOPS mode and starts providing fairness in terms of number of requests
dispatched. Note that this mode switching takes effect only for group
scheduling. For non-cgroup users nothing should change.

28
Documentation/cgroups/blkio-controller.txt
View File

@ -217,6 +217,7 @@ Details of cgroup files
CFQ sysfs tunable
=================
/sys/block/<disk>/queue/iosched/group_isolation
-----------------------------------------------
If group_isolation=1, it provides stronger isolation between groups at the
expense of throughput. By default group_isolation is 0. In general that
@ -243,6 +244,33 @@ By default one should run with group_isolation=0. If that is not sufficient
and one wants stronger isolation between groups, then set group_isolation=1
but this will come at cost of reduced throughput.
/sys/block/<disk>/queue/iosched/slice_idle
------------------------------------------
On a faster hardware CFQ can be slow, especially with sequential workload.
This happens because CFQ idles on a single queue and single queue might not
drive deeper request queue depths to keep the storage busy. In such scenarios
one can try setting slice_idle=0 and that would switch CFQ to IOPS
(IO operations per second) mode on NCQ supporting hardware.
That means CFQ will not idle between cfq queues of a cfq group and hence be
able to driver higher queue depth and achieve better throughput. That also
means that cfq provides fairness among groups in terms of IOPS and not in
terms of disk time.
/sys/block/<disk>/queue/iosched/group_idle
------------------------------------------
If one disables idling on individual cfq queues and cfq service trees by
setting slice_idle=0, group_idle kicks in. That means CFQ will still idle
on the group in an attempt to provide fairness among groups.
By default group_idle is same as slice_idle and does not do anything if
slice_idle is enabled.
One can experience an overall throughput drop if you have created multiple
groups and put applications in that group which are not driving enough
IO to keep disk busy. In that case set group_idle=0, and CFQ will not idle
on individual groups and throughput should improve.
What works
==========
- Currently only sync IO queues are support. All the buffered writes are

22
Documentation/gpio.txt
View File

@ -109,17 +109,19 @@ use numbers 2000-2063 to identify GPIOs in a bank of I2C GPIO expanders.
If you want to initialize a structure with an invalid GPIO number, use
some negative number (perhaps "-EINVAL"); that will never be valid. To
test if a number could reference a GPIO, you may use this predicate:
test if such number from such a structure could reference a GPIO, you
may use this predicate:
int gpio_is_valid(int number);
A number that's not valid will be rejected by calls which may request
or free GPIOs (see below). Other numbers may also be rejected; for
example, a number might be valid but unused on a given board.
Whether a platform supports multiple GPIO controllers is currently a
platform-specific implementation issue.
example, a number might be valid but temporarily unused on a given board.
Whether a platform supports multiple GPIO controllers is a platform-specific
implementation issue, as are whether that support can leave "holes" in the space
of GPIO numbers, and whether new controllers can be added at runtime. Such issues
can affect things including whether adjacent GPIO numbers are both valid.
Using GPIOs
-----------
@ -480,12 +482,16 @@ To support this framework, a platform's Kconfig will "select" either
ARCH_REQUIRE_GPIOLIB or ARCH_WANT_OPTIONAL_GPIOLIB
and arrange that its <asm/gpio.h> includes <asm-generic/gpio.h> and defines
three functions: gpio_get_value(), gpio_set_value(), and gpio_cansleep().
They may also want to provide a custom value for ARCH_NR_GPIOS.
ARCH_REQUIRE_GPIOLIB means that the gpio-lib code will always get compiled
It may also provide a custom value for ARCH_NR_GPIOS, so that it better
reflects the number of GPIOs in actual use on that platform, without
wasting static table space. (It should count both built-in/SoC GPIOs and
also ones on GPIO expanders.
ARCH_REQUIRE_GPIOLIB means that the gpiolib code will always get compiled
into the kernel on that architecture.
ARCH_WANT_OPTIONAL_GPIOLIB means the gpio-lib code defaults to off and the user
ARCH_WANT_OPTIONAL_GPIOLIB means the gpiolib code defaults to off and the user
can enable it and build it into the kernel optionally.
If neither of these options are selected, the platform does not support

5
Documentation/kernel-doc-nano-HOWTO.txt
View File

@ -345,5 +345,10 @@ documentation, in <filename>, for the functions listed.
section titled <section title> from <filename>.
Spaces are allowed in <section title>; do not quote the <section title>.
!C<filename> is replaced by nothing, but makes the tools check that
all DOC: sections and documented functions, symbols, etc. are used.
This makes sense to use when you use !F/!P only and want to verify
that all documentation is included.
Tim.
*/ <twaugh@redhat.com>

17
Documentation/kernel-parameters.txt
View File

@ -1974,15 +1974,18 @@ and is between 256 and 4096 characters. It is defined in the file
force Enable ASPM even on devices that claim not to support it.
WARNING: Forcing ASPM on may cause system lockups.
pcie_ports= [PCIE] PCIe ports handling:
auto Ask the BIOS whether or not to use native PCIe services
associated with PCIe ports (PME, hot-plug, AER). Use
them only if that is allowed by the BIOS.
native Use native PCIe services associated with PCIe ports
unconditionally.
compat Treat PCIe ports as PCI-to-PCI bridges, disable the PCIe
ports driver.
pcie_pme= [PCIE,PM] Native PCIe PME signaling options:
Format: {auto|force}[,nomsi]
auto Use native PCIe PME signaling if the BIOS allows the
kernel to control PCIe config registers of root ports.
force Use native PCIe PME signaling even if the BIOS refuses
to allow the kernel to control the relevant PCIe config
registers.
nomsi Do not use MSI for native PCIe PME signaling (this makes
all PCIe root ports use INTx for everything).
all PCIe root ports use INTx for all services).
pcmv= [HW,PCMCIA] BadgePAD 4

3
Documentation/lguest/Makefile
View File

@ -1,5 +1,6 @@
# This creates the demonstration utility "lguest" which runs a Linux guest.
CFLAGS:=-m32 -Wall -Wmissing-declarations -Wmissing-prototypes -O3 -I../../include -I../../arch/x86/include -U_FORTIFY_SOURCE
# Missing headers? Add "-I../../include -I../../arch/x86/include"
CFLAGS:=-m32 -Wall -Wmissing-declarations -Wmissing-prototypes -O3 -U_FORTIFY_SOURCE
all: lguest

23
Documentation/lguest/lguest.c
View File

@ -39,14 +39,14 @@
#include <limits.h>
#include <stddef.h>
#include <signal.h>
#include "linux/lguest_launcher.h"
#include "linux/virtio_config.h"
#include "linux/virtio_net.h"
#include "linux/virtio_blk.h"
#include "linux/virtio_console.h"
#include "linux/virtio_rng.h"
#include "linux/virtio_ring.h"
#include "asm/bootparam.h"
#include <linux/virtio_config.h>
#include <linux/virtio_net.h>
#include <linux/virtio_blk.h>
#include <linux/virtio_console.h>
#include <linux/virtio_rng.h>
#include <linux/virtio_ring.h>
#include <asm/bootparam.h>
#include "../../include/linux/lguest_launcher.h"
/*L:110
* We can ignore the 42 include files we need for this program, but I do want
* to draw attention to the use of kernel-style types.
@ -1447,14 +1447,15 @@ static void add_to_bridge(int fd, const char *if_name, const char *br_name)
static void configure_device(int fd, const char *tapif, u32 ipaddr)
{
struct ifreq ifr;
struct sockaddr_in *sin = (struct sockaddr_in *)&ifr.ifr_addr;
struct sockaddr_in sin;
memset(&ifr, 0, sizeof(ifr));
strcpy(ifr.ifr_name, tapif);
/* Don't read these incantations. Just cut & paste them like I did! */
sin->sin_family = AF_INET;
sin->sin_addr.s_addr = htonl(ipaddr);
sin.sin_family = AF_INET;
sin.sin_addr.s_addr = htonl(ipaddr);
memcpy(&ifr.ifr_addr, &sin, sizeof(sin));
if (ioctl(fd, SIOCSIFADDR, &ifr) != 0)
err(1, "Setting %s interface address", tapif);
ifr.ifr_flags = IFF_UP;

3
Documentation/mutex-design.txt
View File

@ -9,7 +9,7 @@ firstly, there's nothing wrong with semaphores. But if the simpler
mutex semantics are sufficient for your code, then there are a couple
of advantages of mutexes:
- 'struct mutex' is smaller on most architectures: .e.g on x86,
- 'struct mutex' is smaller on most architectures: E.g. on x86,
'struct semaphore' is 20 bytes, 'struct mutex' is 16 bytes.
A smaller structure size means less RAM footprint, and better
CPU-cache utilization.
@ -136,3 +136,4 @@ the APIs of 'struct mutex' have been streamlined:
void mutex_lock_nested(struct mutex *lock, unsigned int subclass);
int mutex_lock_interruptible_nested(struct mutex *lock,
unsigned int subclass);
int atomic_dec_and_mutex_lock(atomic_t *cnt, struct mutex *lock);

1
Documentation/sound/alsa/HD-Audio-Models.txt
View File

@ -296,6 +296,7 @@ Conexant 5051
Conexant 5066
=============
laptop Basic Laptop config (default)
hp-laptop HP laptops, e g G60
dell-laptop Dell laptops
dell-vostro Dell Vostro
olpc-xo-1_5 OLPC XO 1.5

47
MAINTAINERS
View File

@ -1445,6 +1445,16 @@ S: Maintained
F: Documentation/video4linux/cafe_ccic
F: drivers/media/video/cafe_ccic*
CAIF NETWORK LAYER
M: Sjur Braendeland <sjur.brandeland@stericsson.com>
L: netdev@vger.kernel.org
S: Supported
F: Documentation/networking/caif/
F: drivers/net/caif/
F: include/linux/caif/
F: include/net/caif/
F: net/caif/
CALGARY x86-64 IOMMU
M: Muli Ben-Yehuda <muli@il.ibm.com>
M: "Jon D. Mason" <jdmason@kudzu.us>
@ -1676,8 +1686,7 @@ F: kernel/cgroup*
F: mm/*cgroup*
CORETEMP HARDWARE MONITORING DRIVER
M: Rudolf Marek <r.marek@assembler.cz>
M: Huaxu Wan <huaxu.wan@intel.com>
M: Fenghua Yu <fenghua.yu@intel.com>
L: lm-sensors@lm-sensors.org
S: Maintained
F: Documentation/hwmon/coretemp
@ -2202,6 +2211,12 @@ L: linux-rdma@vger.kernel.org
S: Supported
F: drivers/infiniband/hw/ehca/
EHEA (IBM pSeries eHEA 10Gb ethernet adapter) DRIVER
M: Breno Leitao <leitao@linux.vnet.ibm.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ehea/
EMBEDDED LINUX
M: Paul Gortmaker <paul.gortmaker@windriver.com>
M: Matt Mackall <mpm@selenic.com>
@ -2297,6 +2312,12 @@ S: Maintained
F: Documentation/hwmon/f71805f
F: drivers/hwmon/f71805f.c
FANOTIFY
M: Eric Paris <eparis@redhat.com>
S: Maintained
F: fs/notify/fanotify/
F: include/linux/fanotify.h
FARSYNC SYNCHRONOUS DRIVER
M: Kevin Curtis <kevin.curtis@farsite.co.uk>
W: http://www.farsite.co.uk/
@ -2776,11 +2797,6 @@ S: Maintained
F: arch/x86/kernel/hpet.c
F: arch/x86/include/asm/hpet.h
HPET: ACPI
M: Bob Picco <bob.picco@hp.com>
S: Maintained
F: drivers/char/hpet.c
HPFS FILESYSTEM
M: Mikulas Patocka <mikulas@artax.karlin.mff.cuni.cz>
W: http://artax.karlin.mff.cuni.cz/~mikulas/vyplody/hpfs/index-e.cgi
@ -3393,7 +3409,7 @@ F: drivers/s390/kvm/
KEXEC
M: Eric Biederman <ebiederm@xmission.com>
W: http://ftp.kernel.org/pub/linux/kernel/people/horms/kexec-tools/
W: http://kernel.org/pub/linux/utils/kernel/kexec/
L: kexec@lists.infradead.org
S: Maintained
F: include/linux/kexec.h
@ -3489,7 +3505,7 @@ LGUEST
M: Rusty Russell <rusty@rustcorp.com.au>
L: lguest@lists.ozlabs.org
W: http://lguest.ozlabs.org/
S: Maintained
S: Odd Fixes
F: Documentation/lguest/
F: arch/x86/lguest/
F: drivers/lguest/
@ -3918,8 +3934,7 @@ F: Documentation/sound/oss/MultiSound
F: sound/oss/msnd*
MULTITECH MULTIPORT CARD (ISICOM)
M: Jiri Slaby <jirislaby@gmail.com>
S: Maintained
S: Orphan
F: drivers/char/isicom.c
F: include/linux/isicom.h
@ -4599,7 +4614,7 @@ F: include/linux/preempt.h
PRISM54 WIRELESS DRIVER
M: "Luis R. Rodriguez" <mcgrof@gmail.com>
L: linux-wireless@vger.kernel.org
W: http://prism54.org
W: http://wireless.kernel.org/en/users/Drivers/p54
S: Obsolete
F: drivers/net/wireless/prism54/
@ -4800,6 +4815,7 @@ RCUTORTURE MODULE
M: Josh Triplett <josh@freedesktop.org>
M: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
S: Supported
T: git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-2.6-rcu.git
F: Documentation/RCU/torture.txt
F: kernel/rcutorture.c
@ -4824,6 +4840,7 @@ M: Dipankar Sarma <dipankar@in.ibm.com>
M: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
W: http://www.rdrop.com/users/paulmck/rclock/
S: Supported
T: git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-2.6-rcu.git
F: Documentation/RCU/
F: include/linux/rcu*
F: include/linux/srcu*
@ -4831,12 +4848,10 @@ F: kernel/rcu*
F: kernel/srcu*
X: kernel/rcutorture.c
REAL TIME CLOCK DRIVER
REAL TIME CLOCK DRIVER (LEGACY)
M: Paul Gortmaker <p_gortmaker@yahoo.com>
S: Maintained
F: Documentation/rtc.txt
F: drivers/rtc/
F: include/linux/rtc.h
F: drivers/char/rtc.c
REAL TIME CLOCK (RTC) SUBSYSTEM
M: Alessandro Zummo <a.zummo@towertech.it>

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 36
EXTRAVERSION = -rc2
EXTRAVERSION = -rc4
NAME = Sheep on Meth
# *DOCUMENTATION*

1
arch/alpha/include/asm/cache.h
View File

@ -17,7 +17,6 @@
# define L1_CACHE_SHIFT 5
#endif
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#endif

6
arch/alpha/kernel/err_marvel.c
View File

@ -109,7 +109,7 @@ marvel_print_err_cyc(u64 err_cyc)
#define IO7__ERR_CYC__CYCLE__M (0x7)
printk("%s Packet In Error: %s\n"
"%s Error in %s, cycle %ld%s%s\n",
"%s Error in %s, cycle %lld%s%s\n",
err_print_prefix,
packet_desc[EXTRACT(err_cyc, IO7__ERR_CYC__PACKET)],
err_print_prefix,
@ -313,7 +313,7 @@ marvel_print_po7_ugbge_sym(u64 ugbge_sym)
}
printk("%s Up Hose Garbage Symptom:\n"
"%s Source Port: %ld - Dest PID: %ld - OpCode: %s\n",
"%s Source Port: %lld - Dest PID: %lld - OpCode: %s\n",
err_print_prefix,
err_print_prefix,
EXTRACT(ugbge_sym, IO7__PO7_UGBGE_SYM__UPH_SRC_PORT),
@ -552,7 +552,7 @@ marvel_print_pox_spl_cmplt(u64 spl_cmplt)
#define IO7__POX_SPLCMPLT__REM_BYTE_COUNT__M (0xfff)
printk("%s Split Completion Error:\n"
"%s Source (Bus:Dev:Func): %ld:%ld:%ld\n",
"%s Source (Bus:Dev:Func): %lld:%lld:%lld\n",
err_print_prefix,
err_print_prefix,
EXTRACT(spl_cmplt, IO7__POX_SPLCMPLT__SOURCE_BUS),

2
arch/alpha/kernel/osf_sys.c
View File

@ -252,7 +252,7 @@ SYSCALL_DEFINE3(osf_statfs, const char __user *, pathname,
retval = user_path(pathname, &path);
if (!retval) {
retval = do_osf_statfs(&path buffer, bufsiz);
retval = do_osf_statfs(&path, buffer, bufsiz);
path_put(&path);
}
return retval;

18
arch/alpha/kernel/perf_event.c
View File

@ -241,20 +241,20 @@ static inline unsigned long alpha_read_pmc(int idx)
static int alpha_perf_event_set_period(struct perf_event *event,
struct hw_perf_event *hwc, int idx)
{
long left = atomic64_read(&hwc->period_left);
long left = local64_read(&hwc->period_left);
long period = hwc->sample_period;
int ret = 0;
if (unlikely(left <= -period)) {
left = period;
atomic64_set(&hwc->period_left, left);
local64_set(&hwc->period_left, left);
hwc->last_period = period;
ret = 1;
}
if (unlikely(left <= 0)) {
left += period;
atomic64_set(&hwc->period_left, left);
local64_set(&hwc->period_left, left);
hwc->last_period = period;
ret = 1;
}
@ -269,7 +269,7 @@ static int alpha_perf_event_set_period(struct perf_event *event,
if (left > (long)alpha_pmu->pmc_max_period[idx])
left = alpha_pmu->pmc_max_period[idx];
atomic64_set(&hwc->prev_count, (unsigned long)(-left));
local64_set(&hwc->prev_count, (unsigned long)(-left));
alpha_write_pmc(idx, (unsigned long)(-left));
@ -300,10 +300,10 @@ static unsigned long alpha_perf_event_update(struct perf_event *event,
long delta;
again:
prev_raw_count = atomic64_read(&hwc->prev_count);
prev_raw_count = local64_read(&hwc->prev_count);
new_raw_count = alpha_read_pmc(idx);
if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
new_raw_count) != prev_raw_count)
goto again;
@ -316,8 +316,8 @@ again:
delta += alpha_pmu->pmc_max_period[idx] + 1;
}
atomic64_add(delta, &event->count);
atomic64_sub(delta, &hwc->period_left);
local64_add(delta, &event->count);
local64_sub(delta, &hwc->period_left);
return new_raw_count;
}
@ -670,7 +670,7 @@ static int __hw_perf_event_init(struct perf_event *event)
if (!hwc->sample_period) {
hwc->sample_period = alpha_pmu->pmc_max_period[0];
hwc->last_period = hwc->sample_period;
atomic64_set(&hwc->period_left, hwc->sample_period);
local64_set(&hwc->period_left, hwc->sample_period);
}
return 0;

3
arch/alpha/kernel/proto.h
View File

@ -156,9 +156,6 @@ extern void SMC669_Init(int);
/* es1888.c */
extern void es1888_init(void);
/* ns87312.c */
extern void ns87312_enable_ide(long ide_base);
/* ../lib/fpreg.c */
extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
extern unsigned long alpha_read_fp_reg (unsigned long reg);

19
arch/alpha/kernel/sys_cabriolet.c
View File

@ -33,7 +33,7 @@
#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
#include "pc873xx.h"
/* Note mask bit is true for DISABLED irqs. */
static unsigned long cached_irq_mask = ~0UL;
@ -235,18 +235,31 @@ cabriolet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
return COMMON_TABLE_LOOKUP;
}
static inline void __init
cabriolet_enable_ide(void)
{
if (pc873xx_probe() == -1) {
printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
} else {
printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
pc873xx_get_model(), pc873xx_get_base());
pc873xx_enable_ide();
}
}
static inline void __init
cabriolet_init_pci(void)
{
common_init_pci();
ns87312_enable_ide(0x398);
cabriolet_enable_ide();
}
static inline void __init
cia_cab_init_pci(void)
{
cia_init_pci();
ns87312_enable_ide(0x398);
cabriolet_enable_ide();
}
/*

11
arch/alpha/kernel/sys_takara.c
View File

@ -29,7 +29,7 @@
#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
#include "pc873xx.h"
/* Note mask bit is true for DISABLED irqs. */
static unsigned long cached_irq_mask[2] = { -1, -1 };
@ -264,7 +264,14 @@ takara_init_pci(void)
alpha_mv.pci_map_irq = takara_map_irq_srm;
cia_init_pci();
ns87312_enable_ide(0x26e);
if (pc873xx_probe() == -1) {
printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
} else {
printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
pc873xx_get_model(), pc873xx_get_base());
pc873xx_enable_ide();
}
}

89
arch/arm/Kconfig
View File

@ -1576,95 +1576,6 @@ config AUTO_ZRELADDR
0xf8000000. This assumes the zImage being placed in the first 128MB
from start of memory.
config ZRELADDR
hex "Physical address of the decompressed kernel image"
depends on !AUTO_ZRELADDR
default 0x00008000 if ARCH_BCMRING ||\
ARCH_CNS3XXX ||\
ARCH_DOVE ||\
ARCH_EBSA110 ||\
ARCH_FOOTBRIDGE ||\
ARCH_INTEGRATOR ||\
ARCH_IOP13XX ||\
ARCH_IOP33X ||\
ARCH_IXP2000 ||\
ARCH_IXP23XX ||\
ARCH_IXP4XX ||\
ARCH_KIRKWOOD ||\
ARCH_KS8695 ||\
ARCH_LOKI ||\
ARCH_MMP ||\
ARCH_MV78XX0 ||\
ARCH_NOMADIK ||\
ARCH_NUC93X ||\
ARCH_NS9XXX ||\
ARCH_ORION5X ||\
ARCH_SPEAR3XX ||\
ARCH_SPEAR6XX ||\
ARCH_U8500 ||\
ARCH_VERSATILE ||\
ARCH_W90X900
default 0x08008000 if ARCH_MX1 ||\
ARCH_SHARK
default 0x10008000 if ARCH_MSM ||\
ARCH_OMAP1 ||\
ARCH_RPC
default 0x20008000 if ARCH_S5P6440 ||\
ARCH_S5P6442 ||\
ARCH_S5PC100 ||\
ARCH_S5PV210
default 0x30008000 if ARCH_S3C2410 ||\
ARCH_S3C2400 ||\
ARCH_S3C2412 ||\
ARCH_S3C2416 ||\
ARCH_S3C2440 ||\
ARCH_S3C2443
default 0x40008000 if ARCH_STMP378X ||\
ARCH_STMP37XX ||\
ARCH_SH7372 ||\
ARCH_SH7377
default 0x50008000 if ARCH_S3C64XX ||\
ARCH_SH7367
default 0x60008000 if ARCH_VEXPRESS
default 0x80008000 if ARCH_MX25 ||\
ARCH_MX3 ||\
ARCH_NETX ||\
ARCH_OMAP2PLUS ||\
ARCH_PNX4008
default 0x90008000 if ARCH_MX5 ||\
ARCH_MX91231
default 0xa0008000 if ARCH_IOP32X ||\
ARCH_PXA ||\
MACH_MX27
default 0xc0008000 if ARCH_LH7A40X ||\
MACH_MX21
default 0xf0008000 if ARCH_AAEC2000 ||\
ARCH_L7200
default 0xc0028000 if ARCH_CLPS711X
default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX
default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX
default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET
default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET
default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET
default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET
default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET
default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP
default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP
default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET
default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET
default 0xc0208000 if ARCH_SA1100 && SA1111
default 0xc0008000 if ARCH_SA1100 && !SA1111
default 0x30108000 if ARCH_S3C2410 && PM_H1940
default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM
default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM
help
ZRELADDR is the physical address where the decompressed kernel
image will be placed. ZRELADDR has to be specified when the
assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is
selected.
endmenu
menu "CPU Power Management"

8
arch/arm/boot/Makefile
View File

@ -14,16 +14,18 @@
MKIMAGE := $(srctree)/scripts/mkuboot.sh
ifneq ($(MACHINE),)
-include $(srctree)/$(MACHINE)/Makefile.boot
include $(srctree)/$(MACHINE)/Makefile.boot
endif
# Note: the following conditions must always be true:
# ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
# PARAMS_PHYS must be within 4MB of ZRELADDR
# INITRD_PHYS must be in RAM
ZRELADDR := $(zreladdr-y)
PARAMS_PHYS := $(params_phys-y)
INITRD_PHYS := $(initrd_phys-y)
export INITRD_PHYS PARAMS_PHYS
export ZRELADDR INITRD_PHYS PARAMS_PHYS
targets := Image zImage xipImage bootpImage uImage
@ -65,7 +67,7 @@ quiet_cmd_uimage = UIMAGE $@
ifeq ($(CONFIG_ZBOOT_ROM),y)
$(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
else
$(obj)/uImage: LOADADDR=$(CONFIG_ZRELADDR)
$(obj)/uImage: LOADADDR=$(ZRELADDR)
endif
ifeq ($(CONFIG_THUMB2_KERNEL),y)

4
arch/arm/boot/compressed/Makefile
View File

@ -79,6 +79,10 @@ endif
EXTRA_CFLAGS := -fpic -fno-builtin
EXTRA_AFLAGS := -Wa,-march=all
# Supply ZRELADDR to the decompressor via a linker symbol.
ifneq ($(CONFIG_AUTO_ZRELADDR),y)
LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
endif
ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
LDFLAGS_vmlinux += --be8
endif

2
arch/arm/boot/compressed/head.S
View File

@ -177,7 +177,7 @@ not_angel:
and r4, pc, #0xf8000000
add r4, r4, #TEXT_OFFSET
#else
ldr r4, =CONFIG_ZRELADDR
ldr r4, =zreladdr
#endif
subs r0, r0, r1 @ calculate the delta offset

8
arch/arm/common/it8152.c
View File

@ -263,6 +263,14 @@ static int it8152_pci_platform_notify_remove(struct device *dev)
return 0;
}
int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
{
dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
__func__, dma_addr, size);
return (dev->bus == &pci_bus_type) &&
((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
}
int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
{
it8152_io.start = IT8152_IO_BASE + 0x12000;

3
arch/arm/configs/omap_4430sdp_defconfig
View File

@ -13,6 +13,9 @@ CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_OMAP=y
CONFIG_ARCH_OMAP4=y
# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
# CONFIG_ARCH_OMAP2 is not set
# CONFIG_ARCH_OMAP3 is not set
# CONFIG_OMAP_MUX is not set
CONFIG_OMAP_32K_TIMER=y
CONFIG_OMAP_DM_TIMER=y

8
arch/arm/include/asm/dma-mapping.h
View File

@ -288,15 +288,7 @@ extern void dmabounce_unregister_dev(struct device *);
* DMA access and 1 if the buffer needs to be bounced.
*
*/
#ifdef CONFIG_SA1111
extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
#else
static inline int dma_needs_bounce(struct device *dev, dma_addr_t addr,
size_t size)
{
return 0;
}
#endif
/*
* The DMA API, implemented by dmabounce.c. See below for descriptions.

2
arch/arm/include/asm/perf_event.h
View File

@ -17,7 +17,7 @@
* counter interrupts are regular interrupts and not an NMI. This
* means that when we receive the interrupt we can call
* perf_event_do_pending() that handles all of the work with
* interrupts enabled.
* interrupts disabled.
*/
static inline void
set_perf_event_pending(void)

3
arch/arm/include/asm/unistd.h
View File

@ -393,6 +393,9 @@
#define __NR_perf_event_open (__NR_SYSCALL_BASE+364)
#define __NR_recvmmsg (__NR_SYSCALL_BASE+365)
#define __NR_accept4 (__NR_SYSCALL_BASE+366)
#define __NR_fanotify_init (__NR_SYSCALL_BASE+367)
#define __NR_fanotify_mark (__NR_SYSCALL_BASE+368)
#define __NR_prlimit64 (__NR_SYSCALL_BASE+369)
/*
* The following SWIs are ARM private.

3
arch/arm/kernel/calls.S
View File

@ -376,6 +376,9 @@
CALL(sys_perf_event_open)
/* 365 */ CALL(sys_recvmmsg)
CALL(sys_accept4)
CALL(sys_fanotify_init)
CALL(sys_fanotify_mark)
CALL(sys_prlimit64)
#ifndef syscalls_counted
.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
#define syscalls_counted

2
arch/arm/kernel/etm.c
View File

@ -230,7 +230,7 @@ static void etm_dump(void)
etb_lock(t);
}
static void sysrq_etm_dump(int key, struct tty_struct *tty)
static void sysrq_etm_dump(int key)
{
dev_dbg(tracer.dev, "Dumping ETB buffer\n");
etm_dump();

12
arch/arm/kernel/perf_event.c
View File

@ -342,8 +342,8 @@ validate_event(struct cpu_hw_events *cpuc,
{
struct hw_perf_event fake_event = event->hw;
if (event->pmu && event->pmu != &pmu)
return 0;
if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
return 1;
return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
}
@ -1082,8 +1082,8 @@ armv6pmu_handle_irq(int irq_num,
/*
* Handle the pending perf events.
*
* Note: this call *must* be run with interrupts enabled. For
* platforms that can have the PMU interrupts raised as a PMI, this
* Note: this call *must* be run with interrupts disabled. For
* platforms that can have the PMU interrupts raised as an NMI, this
* will not work.
*/
perf_event_do_pending();
@ -2058,8 +2058,8 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
/*
* Handle the pending perf events.
*
* Note: this call *must* be run with interrupts enabled. For
* platforms that can have the PMU interrupts raised as a PMI, this
* Note: this call *must* be run with interrupts disabled. For
* platforms that can have the PMU interrupts raised as an NMI, this
* will not work.
*/
perf_event_do_pending();

15
arch/arm/mach-at91/at91sam9g45.c
View File

@ -121,8 +121,8 @@ static struct clk ssc1_clk = {
.pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tcb_clk = {
.name = "tcb_clk",
static struct clk tcb0_clk = {
.name = "tcb0_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_TCB,
.type = CLK_TYPE_PERIPHERAL,
};
@ -192,6 +192,14 @@ static struct clk ohci_clk = {
.parent = &uhphs_clk,
};
/* One additional fake clock for second TC block */
static struct clk tcb1_clk = {
.name = "tcb1_clk",
.pmc_mask = 0,
.type = CLK_TYPE_PERIPHERAL,
.parent = &tcb0_clk,
};
static struct clk *periph_clocks[] __initdata = {
&pioA_clk,
&pioB_clk,
@ -208,7 +216,7 @@ static struct clk *periph_clocks[] __initdata = {
&spi1_clk,
&ssc0_clk,
&ssc1_clk,
&tcb_clk,
&tcb0_clk,
&pwm_clk,
&tsc_clk,
&dma_clk,
@ -221,6 +229,7 @@ static struct clk *periph_clocks[] __initdata = {
&mmc1_clk,
// irq0
&ohci_clk,
&tcb1_clk,
};
/*

6
arch/arm/mach-at91/at91sam9g45_devices.c
View File

@ -46,7 +46,7 @@ static struct resource hdmac_resources[] = {
.end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
[1] = {
.start = AT91SAM9G45_ID_DMA,
.end = AT91SAM9G45_ID_DMA,
.flags = IORESOURCE_IRQ,
@ -835,9 +835,9 @@ static struct platform_device at91sam9g45_tcb1_device = {
static void __init at91_add_device_tc(void)
{
/* this chip has one clock and irq for all six TC channels */
at91_clock_associate("tcb_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
at91_clock_associate("tcb0_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
platform_device_register(&at91sam9g45_tcb0_device);
at91_clock_associate("tcb_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
at91_clock_associate("tcb1_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
platform_device_register(&at91sam9g45_tcb1_device);
}
#else

31
arch/arm/mach-at91/board-sam9261ek.c
View File

@ -93,11 +93,12 @@ static struct resource dm9000_resource[] = {
.start = AT91_PIN_PC11,
.end = AT91_PIN_PC11,
.flags = IORESOURCE_IRQ
| IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE,
}
};
static struct dm9000_plat_data dm9000_platdata = {
.flags = DM9000_PLATF_16BITONLY,
.flags = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
};
static struct platform_device dm9000_device = {
@ -167,17 +168,6 @@ static struct at91_udc_data __initdata ek_udc_data = {
};
/*
* MCI (SD/MMC)
*/
static struct at91_mmc_data __initdata ek_mmc_data = {
.wire4 = 1,
// .det_pin = ... not connected
// .wp_pin = ... not connected
// .vcc_pin = ... not connected
};
/*
* NAND flash
*/
@ -246,6 +236,10 @@ static void __init ek_add_device_nand(void)
at91_add_device_nand(&ek_nand_data);
}
/*
* SPI related devices
*/
#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
/*
* ADS7846 Touchscreen
@ -356,6 +350,19 @@ static struct spi_board_info ek_spi_devices[] = {
#endif
};
#else /* CONFIG_SPI_ATMEL_* */
/* spi0 and mmc/sd share the same PIO pins: cannot be used at the same time */
/*
* MCI (SD/MMC)
* det_pin, wp_pin and vcc_pin are not connected
*/
static struct at91_mmc_data __initdata ek_mmc_data = {
.wire4 = 1,
};
#endif /* CONFIG_SPI_ATMEL_* */
/*
* LCD Controller

3
arch/arm/mach-at91/clock.c
View File

@ -501,7 +501,8 @@ postcore_initcall(at91_clk_debugfs_init);
int __init clk_register(struct clk *clk)
{
if (clk_is_peripheral(clk)) {
clk->parent = &mck;
if (!clk->parent)
clk->parent = &mck;
clk->mode = pmc_periph_mode;
list_add_tail(&clk->node, &clocks);
}

2
arch/arm/mach-ep93xx/clock.c
View File

@ -560,4 +560,4 @@ static int __init ep93xx_clock_init(void)
clkdev_add_table(clocks, ARRAY_SIZE(clocks));
return 0;
}
arch_initcall(ep93xx_clock_init);
postcore_initcall(ep93xx_clock_init);

2
arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
View File

@ -215,7 +215,7 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
* Add platform devices present on this baseboard and init
* them from CPU side as far as required to use them later on
*/
void __init eukrea_mbimxsd_baseboard_init(void)
void __init eukrea_mbimxsd25_baseboard_init(void)
{
if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
ARRAY_SIZE(eukrea_mbimxsd_pads)))

4
arch/arm/mach-mx25/mach-cpuimx25.c
View File

@ -147,8 +147,8 @@ static void __init eukrea_cpuimx25_init(void)
if (!otg_mode_host)
mxc_register_device(&otg_udc_device, &otg_device_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
eukrea_mbimxsd_baseboard_init();
#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
eukrea_mbimxsd25_baseboard_init();
#endif
}

77
arch/arm/mach-mx3/clock-imx35.c
View File

@ -155,7 +155,7 @@ static unsigned long get_rate_arm(void)
aad = &clk_consumer[(pdr0 >> 16) & 0xf];
if (aad->sel)
fref = fref * 2 / 3;
fref = fref * 3 / 4;
return fref / aad->arm;
}
@ -164,7 +164,7 @@ static unsigned long get_rate_ahb(struct clk *clk)
{
unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
struct arm_ahb_div *aad;
unsigned long fref = get_rate_mpll();
unsigned long fref = get_rate_arm();
aad = &clk_consumer[(pdr0 >> 16) & 0xf];
@ -176,16 +176,11 @@ static unsigned long get_rate_ipg(struct clk *clk)
return get_rate_ahb(NULL) >> 1;
}
static unsigned long get_3_3_div(unsigned long in)
{
return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1);
}
static unsigned long get_rate_uart(struct clk *clk)
{
unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
unsigned long div = get_3_3_div(pdr4 >> 10);
unsigned long div = ((pdr4 >> 10) & 0x3f) + 1;
if (pdr3 & (1 << 14))
return get_rate_arm() / div;
@ -216,7 +211,7 @@ static unsigned long get_rate_sdhc(struct clk *clk)
break;
}
return rate / get_3_3_div(div);
return rate / (div + 1);
}
static unsigned long get_rate_mshc(struct clk *clk)
@ -270,7 +265,7 @@ static unsigned long get_rate_csi(struct clk *clk)
else
rate = get_rate_ppll();
return rate / get_3_3_div((pdr2 >> 16) & 0x3f);
return rate / (((pdr2 >> 16) & 0x3f) + 1);
}
static unsigned long get_rate_otg(struct clk *clk)
@ -283,25 +278,51 @@ static unsigned long get_rate_otg(struct clk *clk)
else
rate = get_rate_ppll();
return rate / get_3_3_div((pdr4 >> 22) & 0x3f);
return rate / (((pdr4 >> 22) & 0x3f) + 1);
}
static unsigned long get_rate_ipg_per(struct clk *clk)
{
unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
unsigned long div1, div2;
unsigned long div;
if (pdr0 & (1 << 26)) {
div1 = (pdr4 >> 19) & 0x7;
div2 = (pdr4 >> 16) & 0x7;
return get_rate_arm() / ((div1 + 1) * (div2 + 1));
div = (pdr4 >> 16) & 0x3f;
return get_rate_arm() / (div + 1);
} else {
div1 = (pdr0 >> 12) & 0x7;
return get_rate_ahb(NULL) / div1;
div = (pdr0 >> 12) & 0x7;
return get_rate_ahb(NULL) / (div + 1);
}
}
static unsigned long get_rate_hsp(struct clk *clk)
{
unsigned long hsp_podf = (__raw_readl(CCM_BASE + CCM_PDR0) >> 20) & 0x03;
unsigned long fref = get_rate_mpll();
if (fref > 400 * 1000 * 1000) {
switch (hsp_podf) {
case 0:
return fref >> 2;
case 1:
return fref >> 3;
case 2:
return fref / 3;
}
} else {
switch (hsp_podf) {
case 0:
case 2:
return fref / 3;
case 1:
return fref / 6;
}
}
return 0;
}
static int clk_cgr_enable(struct clk *clk)
{
u32 reg;
@ -359,7 +380,7 @@ DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, get_rate_ahb, NULL);
DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, get_rate_hsp, NULL);
DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL);
DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL);
DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL);
@ -485,10 +506,10 @@ static struct clk_lookup lookups[] = {
int __init mx35_clocks_init()
{
unsigned int ll = 0;
unsigned int cgr2 = 3 << 26, cgr3 = 0;
#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
ll = (3 << 16);
cgr2 |= 3 << 16;
#endif
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
@ -499,8 +520,20 @@ int __init mx35_clocks_init()
__raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
__raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
CCM_BASE + CCM_CGR1);
__raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);
__raw_writel(0, CCM_BASE + CCM_CGR3);
/*
* Check if we came up in internal boot mode. If yes, we need some
* extra clocks turned on, otherwise the MX35 boot ROM code will
* hang after a watchdog reset.
*/
if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) {
/* Additionally turn on UART1, SCC, and IIM clocks */
cgr2 |= 3 << 16 | 3 << 4;
cgr3 |= 3 << 2;
}
__raw_writel(cgr2, CCM_BASE + CCM_CGR2);
__raw_writel(cgr3, CCM_BASE + CCM_CGR3);
mxc_timer_init(&gpt_clk,
MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);

2
arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
View File

@ -216,7 +216,7 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
* Add platform devices present on this baseboard and init
* them from CPU side as far as required to use them later on
*/
void __init eukrea_mbimxsd_baseboard_init(void)
void __init eukrea_mbimxsd35_baseboard_init(void)
{
if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
ARRAY_SIZE(eukrea_mbimxsd_pads)))

4
arch/arm/mach-mx3/mach-cpuimx35.c
View File

@ -201,8 +201,8 @@ static void __init mxc_board_init(void)
if (!otg_mode_host)
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
eukrea_mbimxsd_baseboard_init();
#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
eukrea_mbimxsd35_baseboard_init();
#endif
}

2
arch/arm/mach-mx5/clock-mx51.c
View File

@ -56,7 +56,7 @@ static void _clk_ccgr_disable(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift);
reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
}

1
arch/arm/mach-omap2/Makefile
View File

@ -25,6 +25,7 @@ obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o
obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a
AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a
# Functions loaded to SRAM

14
arch/arm/mach-omap2/clock3xxx_data.c
View File

@ -3417,7 +3417,13 @@ int __init omap3xxx_clk_init(void)
struct omap_clk *c;
u32 cpu_clkflg = CK_3XXX;
if (cpu_is_omap34xx()) {
if (cpu_is_omap3517()) {
cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3517;
} else if (cpu_is_omap3505()) {
cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3505;
} else if (cpu_is_omap34xx()) {
cpu_mask = RATE_IN_3XXX;
cpu_clkflg |= CK_343X;
@ -3432,12 +3438,6 @@ int __init omap3xxx_clk_init(void)
cpu_mask |= RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3430ES2;
}
} else if (cpu_is_omap3517()) {
cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3517;
} else if (cpu_is_omap3505()) {
cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3505;
}
if (omap3_has_192mhz_clk())

2
arch/arm/mach-omap2/id.c
View File

@ -284,8 +284,8 @@ static void __init omap3_check_revision(void)
default:
omap_revision = OMAP3630_REV_ES1_2;
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
break;
}
break;
default:
/* Unknown default to latest silicon rev as default*/
omap_revision = OMAP3630_REV_ES1_2;

6
arch/arm/mach-omap2/include/mach/entry-macro.S
View File

@ -177,7 +177,10 @@ omap_irq_base: .word 0
cmpne \irqnr, \tmp
cmpcs \irqnr, \irqnr
.endm
#endif
#endif /* MULTI_OMAP2 */
#ifdef CONFIG_SMP
/* We assume that irqstat (the raw value of the IRQ acknowledge
* register) is preserved from the macro above.
* If there is an IPI, we immediately signal end of interrupt
@ -205,8 +208,7 @@ omap_irq_base: .word 0
streq \irqstat, [\base, #GIC_CPU_EOI]
cmp \tmp, #0
.endm
#endif
#endif /* MULTI_OMAP2 */
#endif /* CONFIG_SMP */
.macro irq_prio_table
.endm

3
arch/arm/mach-omap2/omap-smp.c
View File

@ -102,8 +102,7 @@ static void __init wakeup_secondary(void)
* Send a 'sev' to wake the secondary core from WFE.
* Drain the outstanding writes to memory
*/
dsb();
set_event();
dsb_sev();
mb();
}

4
arch/arm/mach-omap2/pm34xx.c
View File

@ -480,7 +480,9 @@ void omap_sram_idle(void)
}
/* Disable IO-PAD and IO-CHAIN wakeup */
if (omap3_has_io_wakeup() && core_next_state < PWRDM_POWER_ON) {
if (omap3_has_io_wakeup() &&
(per_next_state < PWRDM_POWER_ON ||
core_next_state < PWRDM_POWER_ON)) {
prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
omap3_disable_io_chain();
}

2
arch/arm/mach-pxa/cpufreq-pxa2xx.c
View File

@ -398,7 +398,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
return 0;
}
static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
static int pxa_cpufreq_init(struct cpufreq_policy *policy)
{
int i;
unsigned int freq;

2
arch/arm/mach-pxa/cpufreq-pxa3xx.c
View File

@ -204,7 +204,7 @@ static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
return 0;
}
static __init int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
{
int ret = -EINVAL;

4
arch/arm/mach-pxa/include/mach/mfp-pxa300.h
View File

@ -71,10 +71,10 @@
#define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X)
#define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X)
#define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X)
#define GPIO52_CI_HSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X)
#define GPIO51_CI_VSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X)
#define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X)
#define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X)
#define GPIO51_CI_HSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X)
#define GPIO52_CI_VSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X)
/* KEYPAD */
#define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT)

2
arch/arm/mach-s3c2410/include/mach/vmalloc.h
View File

@ -15,6 +15,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END 0xE0000000UL
#endif /* __ASM_ARCH_VMALLOC_H */

2
arch/arm/mach-s3c64xx/include/mach/vmalloc.h
View File

@ -15,6 +15,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END 0xE0000000UL
#endif /* __ASM_ARCH_VMALLOC_H */

2
arch/arm/mach-s5p6440/include/mach/vmalloc.h
View File

@ -12,6 +12,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END 0xE0000000UL
#endif /* __ASM_ARCH_VMALLOC_H */

2
arch/arm/mach-s5p6442/include/mach/vmalloc.h
View File

@ -12,6 +12,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END 0xE0000000UL
#endif /* __ASM_ARCH_VMALLOC_H */

2
arch/arm/mach-s5pv210/include/mach/vmalloc.h
View File

@ -17,6 +17,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H __FILE__
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END (0xE0000000UL)
#endif /* __ASM_ARCH_VMALLOC_H */

82
arch/arm/mach-s5pv310/clock.c
View File

@ -30,6 +30,16 @@ static struct clk clk_sclk_hdmi27m = {
.rate = 27000000,
};
static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
}
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
}
/* Core list of CMU_CPU side */
static struct clksrc_clk clk_mout_apll = {
@ -39,6 +49,14 @@ static struct clksrc_clk clk_mout_apll = {
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
};
static struct clksrc_clk clk_sclk_apll = {
.clk = {
.name = "sclk_apll",
.id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
};
@ -61,7 +79,7 @@ static struct clksrc_clk clk_mout_mpll = {
};
static struct clk *clkset_moutcore_list[] = {
[0] = &clk_mout_apll.clk,
[0] = &clk_sclk_apll.clk,
[1] = &clk_mout_mpll.clk,
};
@ -154,7 +172,7 @@ static struct clksrc_clk clk_pclk_dbg = {
static struct clk *clkset_corebus_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_mout_apll.clk,
[1] = &clk_sclk_apll.clk,
};
static struct clksrc_sources clkset_mout_corebus = {
@ -220,7 +238,7 @@ static struct clksrc_clk clk_pclk_acp = {
static struct clk *clkset_aclk_top_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_mout_apll.clk,
[1] = &clk_sclk_apll.clk,
};
static struct clksrc_sources clkset_aclk_200 = {
@ -321,11 +339,6 @@ static struct clksrc_clk clk_sclk_vpll = {
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
};
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
}
static struct clk init_clocks_disable[] = {
{
.name = "timers",
@ -337,7 +350,37 @@ static struct clk init_clocks_disable[] = {
};
static struct clk init_clocks[] = {
/* Nothing here yet */
{
.name = "uart",
.id = 0,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
.id = 1,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.id = 2,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
.id = 3,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
.id = 4,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "uart",
.id = 5,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 5),
}
};
static struct clk *clkset_group_list[] = {
@ -359,8 +402,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 0,
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0),
.enable = s5pv310_clk_ip_peril_ctrl,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
@ -369,8 +412,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 1,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 4),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
@ -379,8 +422,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 2,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 8),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
@ -389,8 +432,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 3,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 12),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
@ -399,7 +442,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_pwm",
.id = -1,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &clkset_group,
@ -411,6 +454,7 @@ static struct clksrc_clk clksrcs[] = {
/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
&clk_sclk_apll,
&clk_mout_epll,
&clk_mout_mpll,
&clk_moutcore,
@ -470,11 +514,11 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
__raw_readl(S5P_EPLL_CON1), pll_4500);
__raw_readl(S5P_EPLL_CON1), pll_4600);
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
__raw_readl(S5P_VPLL_CON1), pll_4502);
__raw_readl(S5P_VPLL_CON1), pll_4650);
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;

10
arch/arm/mach-s5pv310/cpu.c
View File

@ -45,6 +45,16 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
.pfn = __phys_to_pfn(S5PV310_PA_L2CC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SYSRAM,
.pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_CMU,
.pfn = __phys_to_pfn(S5PV310_PA_CMU),
.length = SZ_128K,
.type = MT_DEVICE,
},
};

11
arch/arm/mach-s5pv310/include/mach/irqs.h
View File

@ -15,12 +15,14 @@
#include <plat/irqs.h>
/* Private Peripheral Interrupt */
/* PPI: Private Peripheral Interrupt */
#define IRQ_PPI(x) S5P_IRQ(x+16)
#define IRQ_LOCALTIMER IRQ_PPI(13)
/* Shared Peripheral Interrupt */
/* SPI: Shared Peripheral Interrupt */
#define IRQ_SPI(x) S5P_IRQ(x+32)
#define IRQ_EINT0 IRQ_SPI(40)
@ -36,7 +38,7 @@
#define IRQ_PCIE IRQ_SPI(50)
#define IRQ_SYSTEM_TIMER IRQ_SPI(51)
#define IRQ_MFC IRQ_SPI(52)
#define IRQ_WTD IRQ_SPI(53)
#define IRQ_WDT IRQ_SPI(53)
#define IRQ_AUDIO_SS IRQ_SPI(54)
#define IRQ_AC97 IRQ_SPI(55)
#define IRQ_SPDIF IRQ_SPI(56)
@ -67,8 +69,9 @@
#define IRQ_IIC COMBINER_IRQ(27, 0)
/* Set the default NR_IRQS */
#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0)
#define MAX_COMBINER_NR 39
#endif /* ASM_ARCH_IRQS_H */
#endif /* __ASM_ARCH_IRQS_H */

16
arch/arm/mach-s5pv310/include/mach/map.h
View File

@ -23,12 +23,16 @@
#include <plat/map-s5p.h>
#define S5PV310_PA_SYSRAM (0x02025000)
#define S5PV310_PA_CHIPID (0x10000000)
#define S5P_PA_CHIPID S5PV310_PA_CHIPID
#define S5PV310_PA_SYSCON (0x10020000)
#define S5P_PA_SYSCON S5PV310_PA_SYSCON
#define S5PV310_PA_CMU (0x10030000)
#define S5PV310_PA_WATCHDOG (0x10060000)
#define S5PV310_PA_COMBINER (0x10448000)
@ -39,8 +43,12 @@
#define S5PV310_PA_GIC_DIST (0x10501000)
#define S5PV310_PA_L2CC (0x10502000)
#define S5PV310_PA_GPIO (0x11000000)
#define S5P_PA_GPIO S5PV310_PA_GPIO
#define S5PV310_PA_GPIO1 (0x11400000)
#define S5PV310_PA_GPIO2 (0x11000000)
#define S5PV310_PA_GPIO3 (0x03860000)
#define S5P_PA_GPIO S5PV310_PA_GPIO1
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define S5PV310_PA_UART (0x13800000)
@ -63,6 +71,10 @@
/* compatibiltiy defines. */
#define S3C_PA_UART S5PV310_PA_UART
#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
#define S3C_PA_IIC S5PV310_PA_IIC0
#define S3C_PA_WDT S5PV310_PA_WATCHDOG

59
arch/arm/mach-s5pv310/include/mach/regs-clock.h
View File

@ -15,48 +15,49 @@
#include <mach/map.h>
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
#define S5P_INFORM0 S5P_CLKREG(0x800)
#define S5P_EPLL_CON0 S5P_CLKREG(0x1C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x1C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x1C120)
#define S5P_VPLL_CON1 S5P_CLKREG(0x1C124)
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x1C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x1C214)
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x1C250)
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
#define S5P_CLKDIV_TOP S5P_CLKREG(0x1C510)
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x1C550)
#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x1C554)
#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x1C558)
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x1C55C)
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x1C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x1C564)
#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x1C950)
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
#define S5P_CLKSRC_CORE S5P_CLKREG(0x20200)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x20500)
#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500)
#define S5P_APLL_LOCK S5P_CLKREG(0x24000)
#define S5P_MPLL_LOCK S5P_CLKREG(0x24004)
#define S5P_APLL_CON0 S5P_CLKREG(0x24100)
#define S5P_APLL_CON1 S5P_CLKREG(0x24104)
#define S5P_MPLL_CON0 S5P_CLKREG(0x24108)
#define S5P_MPLL_CON1 S5P_CLKREG(0x2410C)
#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
#define S5P_MPLL_CON0 S5P_CLKREG(0x14108)
#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C)
#define S5P_CLKSRC_CPU S5P_CLKREG(0x24200)
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x24400)
#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
#define S5P_CLKDIV_CPU S5P_CLKREG(0x24500)
#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x24600)
#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x24800)
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
#endif /* __ASM_ARCH_REGS_CLOCK_H */

2
arch/arm/mach-s5pv310/include/mach/vmalloc.h
View File

@ -17,6 +17,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H __FILE__
#define VMALLOC_END (0xF0000000)
#define VMALLOC_END (0xF0000000UL)
#endif /* __ASM_ARCH_VMALLOC_H */

2
arch/arm/mach-s5pv310/platsmp.c
View File

@ -187,6 +187,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
__raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_INFORM0);
__raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM);
}
}

2
arch/arm/mach-shmobile/Makefile
View File

@ -3,7 +3,7 @@
#
# Common objects
obj-y := timer.o console.o clock.o
obj-y := timer.o console.o clock.o pm_runtime.o
# CPU objects
obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o

56
arch/arm/mach-shmobile/board-ap4evb.c
View File

@ -25,6 +25,7 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/mfd/sh_mobile_sdhi.h>
#include <linux/mfd/tmio.h>
#include <linux/mmc/host.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
@ -39,6 +40,7 @@
#include <linux/sh_clk.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/leds.h>
#include <linux/input/sh_keysc.h>
#include <linux/usb/r8a66597.h>
@ -307,6 +309,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
.tmio_ocr_mask = MMC_VDD_165_195,
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
};
static struct resource sdhi1_resources[] = {
@ -558,7 +561,7 @@ static struct resource fsi_resources[] = {
static struct platform_device fsi_device = {
.name = "sh_fsi2",
.id = 0,
.id = -1,
.num_resources = ARRAY_SIZE(fsi_resources),
.resource = fsi_resources,
.dev = {
@ -650,7 +653,44 @@ static struct platform_device hdmi_device = {
},
};
static struct gpio_led ap4evb_leds[] = {
{
.name = "led4",
.gpio = GPIO_PORT185,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led2",
.gpio = GPIO_PORT186,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led3",
.gpio = GPIO_PORT187,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led1",
.gpio = GPIO_PORT188,
.default_state = LEDS_GPIO_DEFSTATE_ON,
}
};
static struct gpio_led_platform_data ap4evb_leds_pdata = {
.num_leds = ARRAY_SIZE(ap4evb_leds),
.leds = ap4evb_leds,
};
static struct platform_device leds_device = {
.name = "leds-gpio",
.id = 0,
.dev = {
.platform_data = &ap4evb_leds_pdata,
},
};
static struct platform_device *ap4evb_devices[] __initdata = {
&leds_device,
&nor_flash_device,
&smc911x_device,
&sdhi0_device,
@ -840,20 +880,6 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_CS5A, NULL);
gpio_request(GPIO_FN_IRQ6_39, NULL);
/* enable LED 1 - 4 */
gpio_request(GPIO_PORT185, NULL);
gpio_request(GPIO_PORT186, NULL);
gpio_request(GPIO_PORT187, NULL);
gpio_request(GPIO_PORT188, NULL);
gpio_direction_output(GPIO_PORT185, 1);
gpio_direction_output(GPIO_PORT186, 1);
gpio_direction_output(GPIO_PORT187, 1);
gpio_direction_output(GPIO_PORT188, 1);
gpio_export(GPIO_PORT185, 0);
gpio_export(GPIO_PORT186, 0);
gpio_export(GPIO_PORT187, 0);
gpio_export(GPIO_PORT188, 0);
/* enable Debug switch (S6) */
gpio_request(GPIO_PORT32, NULL);
gpio_request(GPIO_PORT33, NULL);

9
arch/arm/mach-shmobile/clock-sh7372.c
View File

@ -286,7 +286,6 @@ static struct clk_ops pllc2_clk_ops = {
struct clk pllc2_clk = {
.ops = &pllc2_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &extal1_div2_clk,
.freq_table = pllc2_freq_table,
.parent_table = pllc2_parent,
@ -395,7 +394,7 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
enum { MSTP001,
MSTP131, MSTP130,
MSTP129, MSTP128,
MSTP129, MSTP128, MSTP127, MSTP126,
MSTP118, MSTP117, MSTP116,
MSTP106, MSTP101, MSTP100,
MSTP223,
@ -413,6 +412,8 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
[MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
[MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
[MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
[MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
[MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
@ -428,7 +429,7 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
[MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, CLK_ENABLE_ON_INIT), /* FSIA */
[MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSIA */
[MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
[MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
[MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
@ -498,6 +499,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */

4
arch/arm/mach-shmobile/clock.c
View File

@ -1,8 +1,10 @@
/*
* SH-Mobile Timer
* SH-Mobile Clock Framework
*
* Copyright (C) 2010 Magnus Damm
*
* Used together with arch/arm/common/clkdev.c and drivers/sh/clk.c.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.

169
arch/arm/mach-shmobile/pm_runtime.c Normal file
View File

@ -0,0 +1,169 @@
/*
* arch/arm/mach-shmobile/pm_runtime.c
*
* Runtime PM support code for SuperH Mobile ARM
*
* Copyright (C) 2009-2010 Magnus Damm
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/sh_clk.h>
#include <linux/bitmap.h>
#ifdef CONFIG_PM_RUNTIME
#define BIT_ONCE 0
#define BIT_ACTIVE 1
#define BIT_CLK_ENABLED 2
struct pm_runtime_data {
unsigned long flags;
struct clk *clk;
};
static void __devres_release(struct device *dev, void *res)
{
struct pm_runtime_data *prd = res;
dev_dbg(dev, "__devres_release()\n");
if (test_bit(BIT_CLK_ENABLED, &prd->flags))
clk_disable(prd->clk);
if (test_bit(BIT_ACTIVE, &prd->flags))
clk_put(prd->clk);
}
static struct pm_runtime_data *__to_prd(struct device *dev)
{
return devres_find(dev, __devres_release, NULL, NULL);
}
static void platform_pm_runtime_init(struct device *dev,
struct pm_runtime_data *prd)
{
if (prd && !test_and_set_bit(BIT_ONCE, &prd->flags)) {
prd->clk = clk_get(dev, NULL);
if (!IS_ERR(prd->clk)) {
set_bit(BIT_ACTIVE, &prd->flags);
dev_info(dev, "clocks managed by runtime pm\n");
}
}
}
static void platform_pm_runtime_bug(struct device *dev,
struct pm_runtime_data *prd)
{
if (prd && !test_and_set_bit(BIT_ONCE, &prd->flags))
dev_err(dev, "runtime pm suspend before resume\n");
}
int platform_pm_runtime_suspend(struct device *dev)
{
struct pm_runtime_data *prd = __to_prd(dev);
dev_dbg(dev, "platform_pm_runtime_suspend()\n");
platform_pm_runtime_bug(dev, prd);
if (prd && test_bit(BIT_ACTIVE, &prd->flags)) {
clk_disable(prd->clk);
clear_bit(BIT_CLK_ENABLED, &prd->flags);
}
return 0;
}
int platform_pm_runtime_resume(struct device *dev)
{
struct pm_runtime_data *prd = __to_prd(dev);
dev_dbg(dev, "platform_pm_runtime_resume()\n");
platform_pm_runtime_init(dev, prd);
if (prd && test_bit(BIT_ACTIVE, &prd->flags)) {
clk_enable(prd->clk);
set_bit(BIT_CLK_ENABLED, &prd->flags);
}
return 0;
}
int platform_pm_runtime_idle(struct device *dev)
{
/* suspend synchronously to disable clocks immediately */
return pm_runtime_suspend(dev);
}
static int platform_bus_notify(struct notifier_block *nb,
unsigned long action, void *data)
{
struct device *dev = data;
struct pm_runtime_data *prd;
dev_dbg(dev, "platform_bus_notify() %ld !\n", action);
if (action == BUS_NOTIFY_BIND_DRIVER) {
prd = devres_alloc(__devres_release, sizeof(*prd), GFP_KERNEL);
if (prd)
devres_add(dev, prd);
else
dev_err(dev, "unable to alloc memory for runtime pm\n");
}
return 0;
}
#else /* CONFIG_PM_RUNTIME */
static int platform_bus_notify(struct notifier_block *nb,
unsigned long action, void *data)
{
struct device *dev = data;
struct clk *clk;
dev_dbg(dev, "platform_bus_notify() %ld !\n", action);
switch (action) {
case BUS_NOTIFY_BIND_DRIVER:
clk = clk_get(dev, NULL);
if (!IS_ERR(clk)) {
clk_enable(clk);
clk_put(clk);
dev_info(dev, "runtime pm disabled, clock forced on\n");
}
break;
case BUS_NOTIFY_UNBOUND_DRIVER:
clk = clk_get(dev, NULL);
if (!IS_ERR(clk)) {
clk_disable(clk);
clk_put(clk);
dev_info(dev, "runtime pm disabled, clock forced off\n");
}
break;
}
return 0;
}
#endif /* CONFIG_PM_RUNTIME */
static struct notifier_block platform_bus_notifier = {
.notifier_call = platform_bus_notify
};
static int __init sh_pm_runtime_init(void)
{
bus_register_notifier(&platform_bus_type, &platform_bus_notifier);
return 0;
}
core_initcall(sh_pm_runtime_init);

2
arch/arm/mach-tegra/board-harmony.c
View File

@ -91,10 +91,8 @@ static void __init tegra_harmony_fixup(struct machine_desc *desc,
{
mi->nr_banks = 2;
mi->bank[0].start = PHYS_OFFSET;
mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
mi->bank[0].size = 448 * SZ_1M;
mi->bank[1].start = SZ_512M;
mi->bank[1].node = PHYS_TO_NID(SZ_512M);
mi->bank[1].size = SZ_512M;
}

2
arch/arm/mach-tegra/include/mach/vmalloc.h
View File

@ -23,6 +23,6 @@
#include <asm/sizes.h>
#define VMALLOC_END 0xFE000000
#define VMALLOC_END 0xFE000000UL
#endif

2
arch/arm/mm/Kconfig
View File

@ -398,7 +398,7 @@ config CPU_V6
# ARMv6k
config CPU_32v6K
bool "Support ARM V6K processor extensions" if !SMP
depends on CPU_V6
depends on CPU_V6 || CPU_V7
default y if SMP && !(ARCH_MX3 || ARCH_OMAP2)
help
Say Y here if your ARMv6 processor supports the 'K' extension.

2
arch/arm/mm/dma-mapping.c
View File

@ -229,6 +229,8 @@ __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
}
} while (size -= PAGE_SIZE);
dsb();
return (void *)c->vm_start;
}
return NULL;

1
arch/arm/plat-mxc/Kconfig
View File

@ -43,6 +43,7 @@ config ARCH_MXC91231
config ARCH_MX5
bool "MX5-based"
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
help
This enables support for systems based on the Freescale i.MX51 family

4
arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
View File

@ -37,9 +37,9 @@
* mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
*/
extern void eukrea_mbimx25_baseboard_init(void);
extern void eukrea_mbimxsd25_baseboard_init(void);
extern void eukrea_mbimx27_baseboard_init(void);
extern void eukrea_mbimx35_baseboard_init(void);
extern void eukrea_mbimxsd35_baseboard_init(void);
extern void eukrea_mbimx51_baseboard_init(void);
#endif

5
arch/arm/plat-mxc/tzic.c
View File

@ -164,8 +164,9 @@ int tzic_enable_wake(int is_idle)
return -EAGAIN;
for (i = 0; i < 4; i++) {
v = is_idle ? __raw_readl(TZIC_ENSET0(i)) : wakeup_intr[i];
__raw_writel(v, TZIC_WAKEUP0(i));
v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
wakeup_intr[i];
__raw_writel(v, tzic_base + TZIC_WAKEUP0(i));
}
return 0;

7
arch/arm/plat-omap/include/plat/smp.h
View File

@ -19,13 +19,6 @@
#include <asm/hardware/gic.h>
/*
* set_event() is used to wake up secondary core from wfe using sev. ROM
* code puts the second core into wfe(standby).
*
*/
#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
/* Needed for secondary core boot */
extern void omap_secondary_startup(void);
extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);

2
arch/arm/plat-pxa/pwm.c
View File

@ -176,7 +176,7 @@ static inline void __add_pwm(struct pwm_device *pwm)
static int __devinit pwm_probe(struct platform_device *pdev)
{
struct platform_device_id *id = platform_get_device_id(pdev);
const struct platform_device_id *id = platform_get_device_id(pdev);
struct pwm_device *pwm, *secondary = NULL;
struct resource *r;
int ret = 0;

2
arch/arm/plat-s5p/include/plat/map-s5p.h
View File

@ -17,6 +17,7 @@
#define S5P_VA_GPIO S3C_ADDR(0x00500000)
#define S5P_VA_SYSTIMER S3C_ADDR(0x01200000)
#define S5P_VA_SROMC S3C_ADDR(0x01100000)
#define S5P_VA_SYSRAM S3C_ADDR(0x01180000)
#define S5P_VA_COMBINER_BASE S3C_ADDR(0x00600000)
#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
@ -29,6 +30,7 @@
#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000)
#define S5P_VA_L2CC S3C_ADDR(0x00900000)
#define S5P_VA_CMU S3C_ADDR(0x00920000)
#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_VA_UART0 S5P_VA_UART(0)

98
arch/arm/tools/mach-types
View File

@ -12,7 +12,7 @@
#
# http://www.arm.linux.org.uk/developer/machines/?action=new
#
# Last update: Mon Jul 12 21:10:14 2010
# Last update: Thu Sep 9 22:43:01 2010
#
# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
#
@ -2622,7 +2622,7 @@ kraken MACH_KRAKEN KRAKEN 2634
gw2388 MACH_GW2388 GW2388 2635
jadecpu MACH_JADECPU JADECPU 2636
carlisle MACH_CARLISLE CARLISLE 2637
lux_sf9 MACH_LUX_SFT9 LUX_SFT9 2638
lux_sf9 MACH_LUX_SF9 LUX_SF9 2638
nemid_tb MACH_NEMID_TB NEMID_TB 2639
terrier MACH_TERRIER TERRIER 2640
turbot MACH_TURBOT TURBOT 2641
@ -2950,3 +2950,97 @@ davinci_dm365_dvr MACH_DAVINCI_DM365_DVR DAVINCI_DM365_DVR 2963
netviz MACH_NETVIZ NETVIZ 2964
flexibity MACH_FLEXIBITY FLEXIBITY 2965
wlan_computer MACH_WLAN_COMPUTER WLAN_COMPUTER 2966
lpc24xx MACH_LPC24XX LPC24XX 2967
spica MACH_SPICA SPICA 2968
gpsdisplay MACH_GPSDISPLAY GPSDISPLAY 2969
bipnet MACH_BIPNET BIPNET 2970
overo_ctu_inertial MACH_OVERO_CTU_INERTIAL OVERO_CTU_INERTIAL 2971
davinci_dm355_mmm MACH_DAVINCI_DM355_MMM DAVINCI_DM355_MMM 2972
pc9260_v2 MACH_PC9260_V2 PC9260_V2 2973
ptx7545 MACH_PTX7545 PTX7545 2974
tm_efdc MACH_TM_EFDC TM_EFDC 2975
omap3_waldo1 MACH_OMAP3_WALDO1 OMAP3_WALDO1 2977
flyer MACH_FLYER FLYER 2978
tornado3240 MACH_TORNADO3240 TORNADO3240 2979
soli_01 MACH_SOLI_01 SOLI_01 2980
omapl138_europalc MACH_OMAPL138_EUROPALC OMAPL138_EUROPALC 2981
helios_v1 MACH_HELIOS_V1 HELIOS_V1 2982
netspace_lite_v2 MACH_NETSPACE_LITE_V2 NETSPACE_LITE_V2 2983
ssc MACH_SSC SSC 2984
premierwave_en MACH_PREMIERWAVE_EN PREMIERWAVE_EN 2985
wasabi MACH_WASABI WASABI 2986
vivow MACH_VIVOW VIVOW 2987
mx50_rdp MACH_MX50_RDP MX50_RDP 2988
universal MACH_UNIVERSAL UNIVERSAL 2989
real6410 MACH_REAL6410 REAL6410 2990
spx_sakura MACH_SPX_SAKURA SPX_SAKURA 2991
ij3k_2440 MACH_IJ3K_2440 IJ3K_2440 2992
omap3_bc10 MACH_OMAP3_BC10 OMAP3_BC10 2993
thebe MACH_THEBE THEBE 2994
rv082 MACH_RV082 RV082 2995
armlguest MACH_ARMLGUEST ARMLGUEST 2996
tjinc1000 MACH_TJINC1000 TJINC1000 2997
dockstar MACH_DOCKSTAR DOCKSTAR 2998
ax8008 MACH_AX8008 AX8008 2999
gnet_sgce MACH_GNET_SGCE GNET_SGCE 3000
pxwnas_500_1000 MACH_PXWNAS_500_1000 PXWNAS_500_1000 3001
ea20 MACH_EA20 EA20 3002
awm2 MACH_AWM2 AWM2 3003
ti8148evm MACH_TI8148EVM TI8148EVM 3004
tegra_seaboard MACH_TEGRA_SEABOARD TEGRA_SEABOARD 3005
linkstation_chlv2 MACH_LINKSTATION_CHLV2 LINKSTATION_CHLV2 3006
tera_pro2_rack MACH_TERA_PRO2_RACK TERA_PRO2_RACK 3007
rubys MACH_RUBYS RUBYS 3008
aquarius MACH_AQUARIUS AQUARIUS 3009
mx53_ard MACH_MX53_ARD MX53_ARD 3010
mx53_smd MACH_MX53_SMD MX53_SMD 3011
lswxl MACH_LSWXL LSWXL 3012
dove_avng_v3 MACH_DOVE_AVNG_V3 DOVE_AVNG_V3 3013
sdi_ess_9263 MACH_SDI_ESS_9263 SDI_ESS_9263 3014
jocpu550 MACH_JOCPU550 JOCPU550 3015
msm8x60_rumi3 MACH_MSM8X60_RUMI3 MSM8X60_RUMI3 3016
msm8x60_ffa MACH_MSM8X60_FFA MSM8X60_FFA 3017
yanomami MACH_YANOMAMI YANOMAMI 3018
gta04 MACH_GTA04 GTA04 3019
cm_a510 MACH_CM_A510 CM_A510 3020
omap3_rfs200 MACH_OMAP3_RFS200 OMAP3_RFS200 3021
kx33xx MACH_KX33XX KX33XX 3022
ptx7510 MACH_PTX7510 PTX7510 3023
top9000 MACH_TOP9000 TOP9000 3024
teenote MACH_TEENOTE TEENOTE 3025
ts3 MACH_TS3 TS3 3026
a0 MACH_A0 A0 3027
fsm9xxx_surf MACH_FSM9XXX_SURF FSM9XXX_SURF 3028
fsm9xxx_ffa MACH_FSM9XXX_FFA FSM9XXX_FFA 3029
frrhwcdma60w MACH_FRRHWCDMA60W FRRHWCDMA60W 3030
remus MACH_REMUS REMUS 3031
at91cap7xdk MACH_AT91CAP7XDK AT91CAP7XDK 3032
at91cap7stk MACH_AT91CAP7STK AT91CAP7STK 3033
kt_sbc_sam9_1 MACH_KT_SBC_SAM9_1 KT_SBC_SAM9_1 3034
oratisrouter MACH_ORATISROUTER ORATISROUTER 3035
armada_xp_db MACH_ARMADA_XP_DB ARMADA_XP_DB 3036
spdm MACH_SPDM SPDM 3037
gtib MACH_GTIB GTIB 3038
dgm3240 MACH_DGM3240 DGM3240 3039
atlas_i_lpe MACH_ATLAS_I_LPE ATLAS_I_LPE 3040
htcmega MACH_HTCMEGA HTCMEGA 3041
tricorder MACH_TRICORDER TRICORDER 3042
tx28 MACH_TX28 TX28 3043
bstbrd MACH_BSTBRD BSTBRD 3044
pwb3090 MACH_PWB3090 PWB3090 3045
idea6410 MACH_IDEA6410 IDEA6410 3046
qbc9263 MACH_QBC9263 QBC9263 3047
borabora MACH_BORABORA BORABORA 3048
valdez MACH_VALDEZ VALDEZ 3049
ls9g20 MACH_LS9G20 LS9G20 3050
mios_v1 MACH_MIOS_V1 MIOS_V1 3051
s5pc110_crespo MACH_S5PC110_CRESPO S5PC110_CRESPO 3052
controltek9g20 MACH_CONTROLTEK9G20 CONTROLTEK9G20 3053
tin307 MACH_TIN307 TIN307 3054
tin510 MACH_TIN510 TIN510 3055
bluecheese MACH_BLUECHEESE BLUECHEESE 3057
tem3x30 MACH_TEM3X30 TEM3X30 3058
harvest_desoto MACH_HARVEST_DESOTO HARVEST_DESOTO 3059
msm8x60_qrdc MACH_MSM8X60_QRDC MSM8X60_QRDC 3060
spear900 MACH_SPEAR900 SPEAR900 3061
pcontrol_g20 MACH_PCONTROL_G20 PCONTROL_G20 3062

6
arch/blackfin/include/asm/bfin_sport.h
View File

@ -115,12 +115,6 @@ struct sport_register {
#endif
/* Workaround defBF*.h SPORT MMRs till they get cleansed */
#undef DTYPE_NORM
#undef SLEN
#undef SP_WOFF
#undef SP_WSIZE
/* SPORT_TCR1 Masks */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */

82
arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
View File

@ -913,88 +913,6 @@
#define PH6 0x0040
#define PH7 0x0080
/* ******************* SERIAL PORT MASKS **************************************/
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* Transmit Enable */
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* Transmit Bit Order */
#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_TCR2 Masks and Macro */
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#define TXSE 0x0100 /* TX Secondary Enable */
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* Receive Enable */
#define IRCLK 0x0002 /* Internal Receive Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* Receive Bit Order */
#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
#define RFSR 0x0400 /* Receive Frame Sync Required Select */
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
#define LARFS 0x2000 /* Late Receive Frame Sync Select */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
#define RXSE 0x0100 /* RX Secondary Enable */
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /* Right-First Data Order */
/* SPORTx_STAT Masks */
#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
#define RUVF 0x0002 /* Sticky Receive Underflow Status */
#define ROVF 0x0004 /* Sticky Receive Overflow Status */
#define TXF 0x0008 /* Transmit FIFO Full Status */
#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
/* SPORTx_MCMC1 Macros */
#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
/* SPORTx_MCMC2 Masks */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
/* EBIU_AMGCTL Masks */
#define AMCKEN 0x0001 /* Enable CLKOUT */

1
arch/blackfin/mach-bf527/boards/cm_bf527.c
View File

@ -145,7 +145,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),

1
arch/blackfin/mach-bf527/boards/ezbrd.c
View File

@ -149,7 +149,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),

1
arch/blackfin/mach-bf527/boards/ezkit.c
View File

@ -234,7 +234,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),

82
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
View File

@ -922,88 +922,6 @@
#define PH14 0x4000
#define PH15 0x8000
/* ******************* SERIAL PORT MASKS **************************************/
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* Transmit Enable */
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* Transmit Bit Order */
#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_TCR2 Masks and Macro */
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#define TXSE 0x0100 /* TX Secondary Enable */
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* Receive Enable */
#define IRCLK 0x0002 /* Internal Receive Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* Receive Bit Order */
#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
#define RFSR 0x0400 /* Receive Frame Sync Required Select */
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
#define LARFS 0x2000 /* Late Receive Frame Sync Select */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
#define RXSE 0x0100 /* RX Secondary Enable */
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /* Right-First Data Order */
/* SPORTx_STAT Masks */
#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
#define RUVF 0x0002 /* Sticky Receive Underflow Status */
#define ROVF 0x0004 /* Sticky Receive Overflow Status */
#define TXF 0x0008 /* Transmit FIFO Full Status */
#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
/* SPORTx_MCMC1 Macros */
#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
/* SPORTx_MCMC2 Masks */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
/* EBIU_AMGCTL Masks */
#define AMCKEN 0x0001 /* Enable CLKOUT */

92
arch/blackfin/mach-bf533/include/mach/defBF532.h
View File

@ -509,98 +509,6 @@
#define IREN_P 0x01
#define UCEN_P 0x00
/* ********** SERIAL PORT MASKS ********************** */
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */
#define TDTYPE 0x000C /* TX Data Formatting Select */
#define DTYPE_NORM 0x0000 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* TX Bit Order */
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
#define TFSR 0x0400 /* TX Frame Sync Required Select */
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
#define LTFS 0x1000 /* Low TX Frame Sync Select */
#define LATFS 0x2000 /* Late TX Frame Sync Select */
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
/* SPORTx_TCR2 Masks */
#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
defined(__ADSPBF533__)
# define SLEN 0x001F /*TX Word Length */
#else
# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#endif
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define TRFST 0x0400 /*TX Right-First Data Order */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* RX enable */
#define IRCLK 0x0002 /* Internal RX Clock Select */
#define RDTYPE 0x000C /* RX Data Formatting Select */
#define DTYPE_NORM 0x0000 /* no companding */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* RX Bit Order */
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
#define RFSR 0x0400 /* RX Frame Sync Required Select */
#define LRFS 0x1000 /* Low RX Frame Sync Select */
#define LARFS 0x2000 /* Late RX Frame Sync Select */
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
/* SLEN defined above */
#define RXSE 0x0100 /*RX Secondary Enable */
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /*Right-First Data Order */
/*SPORTx_STAT Masks */
#define RXNE 0x0001 /*RX FIFO Not Empty Status */
#define RUVF 0x0002 /*RX Underflow Status */
#define ROVF 0x0004 /*RX Overflow Status */
#define TXF 0x0008 /*TX FIFO Full Status */
#define TUVF 0x0010 /*TX Underflow Status */
#define TOVF 0x0020 /*TX Overflow Status */
#define TXHRE 0x0040 /*TX Hold Register Empty */
/*SPORTx_MCMC1 Masks */
#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
/* SPORTx_MCMC1 Macros */
#define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
/*SPORTx_MCMC2 Masks */
#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
#define MFD 0x0000F000 /*Multichannel Frame Delay */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
/* PPI_CONTROL Masks */

80
arch/blackfin/mach-bf537/include/mach/defBF534.h
View File

@ -1241,86 +1241,6 @@
#define PH14 0x4000
#define PH15 0x8000
/* ******************* SERIAL PORT MASKS **************************************/
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* Transmit Enable */
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* Transmit Bit Order */
#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_TCR2 Masks and Macro */
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#define TXSE 0x0100 /* TX Secondary Enable */
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* Receive Enable */
#define IRCLK 0x0002 /* Internal Receive Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* Receive Bit Order */
#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
#define RFSR 0x0400 /* Receive Frame Sync Required Select */
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
#define LARFS 0x2000 /* Late Receive Frame Sync Select */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
#define RXSE 0x0100 /* RX Secondary Enable */
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /* Right-First Data Order */
/* SPORTx_STAT Masks */
#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
#define RUVF 0x0002 /* Sticky Receive Underflow Status */
#define ROVF 0x0004 /* Sticky Receive Overflow Status */
#define TXF 0x0008 /* Transmit FIFO Full Status */
#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
/* SPORTx_MCMC1 Macros */
#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
/* SPORTx_MCMC2 Masks */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
/* EBIU_AMGCTL Masks */
#define AMCKEN 0x0001 /* Enable CLKOUT */

107
arch/blackfin/mach-bf538/include/mach/defBF539.h
View File

@ -1610,113 +1610,6 @@
#define UCEN_P 0x00
/* ********** SERIAL PORT MASKS ********************** */
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */
#define TDTYPE 0x000C /* TX Data Formatting Select */
#define DTYPE_NORM 0x0000 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* TX Bit Order */
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
#define TFSR 0x0400 /* TX Frame Sync Required Select */
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
#define LTFS 0x1000 /* Low TX Frame Sync Select */
#define LATFS 0x2000 /* Late TX Frame Sync Select */
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
/* SPORTx_RCR1 Deprecated Masks */
#define TULAW DTYPE_ULAW /* Compand Using u-Law */
#define TALAW DTYPE_ALAW /* Compand Using A-Law */
/* SPORTx_TCR2 Masks */
#ifdef _MISRA_RULES
#define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
#else
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#endif /* _MISRA_RULES */
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define TRFST 0x0400 /*TX Right-First Data Order */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* RX enable */
#define IRCLK 0x0002 /* Internal RX Clock Select */
#define RDTYPE 0x000C /* RX Data Formatting Select */
#define DTYPE_NORM 0x0000 /* no companding */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* RX Bit Order */
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
#define RFSR 0x0400 /* RX Frame Sync Required Select */
#define LRFS 0x1000 /* Low RX Frame Sync Select */
#define LARFS 0x2000 /* Late RX Frame Sync Select */
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
/* SPORTx_RCR1 Deprecated Masks */
#define RULAW DTYPE_ULAW /* Compand Using u-Law */
#define RALAW DTYPE_ALAW /* Compand Using A-Law */
/* SPORTx_RCR2 Masks */
#ifdef _MISRA_RULES
#define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */
#else
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
#endif /* _MISRA_RULES */
#define RXSE 0x0100 /*RX Secondary Enable */
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /*Right-First Data Order */
/*SPORTx_STAT Masks */
#define RXNE 0x0001 /*RX FIFO Not Empty Status */
#define RUVF 0x0002 /*RX Underflow Status */
#define ROVF 0x0004 /*RX Overflow Status */
#define TXF 0x0008 /*TX FIFO Full Status */
#define TUVF 0x0010 /*TX Underflow Status */
#define TOVF 0x0020 /*TX Overflow Status */
#define TXHRE 0x0040 /*TX Hold Register Empty */
/*SPORTx_MCMC1 Masks */
#define WOFF 0x000003FF /*Multichannel Window Offset Field */
/* SPORTx_MCMC1 Macros */
#ifdef _MISRA_RULES
#define SET_WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SET_WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
#else
#define SET_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SET_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
#endif /* _MISRA_RULES */
/*SPORTx_MCMC2 Masks */
#define MCCRM 0x0003 /*Multichannel Clock Recovery Mode */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x0004 /*Multichannel DMA Transmit Packing */
#define MCDRXPE 0x0008 /*Multichannel DMA Receive Packing */
#define MCMEN 0x0010 /*Multichannel Frame Mode Enable */
#define FSDR 0x0080 /*Multichannel Frame Sync to Data Relationship */
#define MFD 0xF000 /*Multichannel Frame Delay */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
/* PPI_CONTROL Masks */
#define PORT_EN 0x0001 /* PPI Port Enable */

1
arch/blackfin/mach-bf548/boards/cm_bf548.c
View File

@ -706,7 +706,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),

1
arch/blackfin/mach-bf548/boards/ezkit.c
View File

@ -849,7 +849,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),

67
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
View File

@ -2221,73 +2221,6 @@
#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
/* Bit masks for SPORTx_TCR1 */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
#define LATFS 0x2000 /* Late Transmit Frame Sync */
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */
#define TFSR 0x400 /* Transmit Frame Sync Required Select */
#define ITFS 0x200 /* Internal Transmit Frame Sync Select */
#define TLSBIT 0x10 /* Transmit Bit Order */
#define TDTYPE 0xc /* Data Formatting Type Select */
#define ITCLK 0x2 /* Internal Transmit Clock Select */
#define TSPEN 0x1 /* Transmit Enable */
/* Bit masks for SPORTx_TCR2 */
#define TRFST 0x400 /* Left/Right Order */
#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */
#define TXSE 0x100 /* TxSEC Enable */
#define SLEN_T 0x1f /* SPORT Word Length */
/* Bit masks for SPORTx_RCR1 */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
#define LARFS 0x2000 /* Late Receive Frame Sync */
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
#define RFSR 0x400 /* Receive Frame Sync Required Select */
#define IRFS 0x200 /* Internal Receive Frame Sync Select */
#define RLSBIT 0x10 /* Receive Bit Order */
#define RDTYPE 0xc /* Data Formatting Type Select */
#define IRCLK 0x2 /* Internal Receive Clock Select */
#define RSPEN 0x1 /* Receive Enable */
/* Bit masks for SPORTx_RCR2 */
#define RRFST 0x400 /* Left/Right Order */
#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */
#define RXSE 0x100 /* RxSEC Enable */
#define SLEN_R 0x1f /* SPORT Word Length */
/* Bit masks for SPORTx_STAT */
#define TXHRE 0x40 /* Transmit Hold Register Empty */
#define TOVF 0x20 /* Sticky Transmit Overflow Status */
#define TUVF 0x10 /* Sticky Transmit Underflow Status */
#define TXF 0x8 /* Transmit FIFO Full Status */
#define ROVF 0x4 /* Sticky Receive Overflow Status */
#define RUVF 0x2 /* Sticky Receive Underflow Status */
#define RXNE 0x1 /* Receive FIFO Not Empty Status */
/* Bit masks for SPORTx_MCMC1 */
#define SP_WSIZE 0xf000 /* Window Size */
#define SP_WOFF 0x3ff /* Windows Offset */
/* Bit masks for SPORTx_MCMC2 */
#define MFD 0xf000 /* Multi channel Frame Delay */
#define FSDR 0x80 /* Frame Sync to Data Relationship */
#define MCMEN 0x10 /* Multi channel Frame Mode Enable */
#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
#define MCCRM 0x3 /* 2X Clock Recovery Mode */
/* Bit masks for SPORTx_CHNL */
#define CUR_CHNL 0x3ff /* Current Channel Indicator */
/* Bit masks for UARTx_LCR */
#if 0

60
arch/blackfin/mach-bf561/include/mach/defBF561.h
View File

@ -1007,66 +1007,6 @@
#define IREN_P 0x01
#define UCEN_P 0x00
/* ********** SERIAL PORT MASKS ********************** */
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */
#define TDTYPE 0x000C /* TX Data Formatting Select */
#define TLSBIT 0x0010 /* TX Bit Order */
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
#define TFSR 0x0400 /* TX Frame Sync Required Select */
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
#define LTFS 0x1000 /* Low TX Frame Sync Select */
#define LATFS 0x2000 /* Late TX Frame Sync Select */
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
/* SPORTx_TCR2 Masks */
#define SLEN 0x001F /*TX Word Length */
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define TRFST 0x0400 /*TX Right-First Data Order */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* RX enable */
#define IRCLK 0x0002 /* Internal RX Clock Select */
#define RDTYPE 0x000C /* RX Data Formatting Select */
#define RULAW 0x0008 /* u-Law enable */
#define RALAW 0x000C /* A-Law enable */
#define RLSBIT 0x0010 /* RX Bit Order */
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
#define RFSR 0x0400 /* RX Frame Sync Required Select */
#define LRFS 0x1000 /* Low RX Frame Sync Select */
#define LARFS 0x2000 /* Late RX Frame Sync Select */
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN 0x001F /*RX Word Length */
#define RXSE 0x0100 /*RX Secondary Enable */
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /*Right-First Data Order */
/*SPORTx_STAT Masks */
#define RXNE 0x0001 /*RX FIFO Not Empty Status */
#define RUVF 0x0002 /*RX Underflow Status */
#define ROVF 0x0004 /*RX Overflow Status */
#define TXF 0x0008 /*TX FIFO Full Status */
#define TUVF 0x0010 /*TX Underflow Status */
#define TOVF 0x0020 /*TX Overflow Status */
#define TXHRE 0x0040 /*TX Hold Register Empty */
/*SPORTx_MCMC1 Masks */
#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
/*SPORTx_MCMC2 Masks */
#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
#define MFD 0x0000F000 /*Multichannel Frame Delay */
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
/* PPI_CONTROL Masks */

15
arch/h8300/include/asm/atomic.h
View File

@ -18,7 +18,8 @@
static __inline__ int atomic_add_return(int i, atomic_t *v)
{
int ret,flags;
unsigned long flags;
int ret;
local_irq_save(flags);
ret = v->counter += i;
local_irq_restore(flags);
@ -30,7 +31,8 @@ static __inline__ int atomic_add_return(int i, atomic_t *v)
static __inline__ int atomic_sub_return(int i, atomic_t *v)
{
int ret,flags;
unsigned long flags;
int ret;
local_irq_save(flags);
ret = v->counter -= i;
local_irq_restore(flags);
@ -42,7 +44,8 @@ static __inline__ int atomic_sub_return(int i, atomic_t *v)
static __inline__ int atomic_inc_return(atomic_t *v)
{
int ret,flags;
unsigned long flags;
int ret;
local_irq_save(flags);
v->counter++;
ret = v->counter;
@ -64,7 +67,8 @@ static __inline__ int atomic_inc_return(atomic_t *v)
static __inline__ int atomic_dec_return(atomic_t *v)
{
int ret,flags;
unsigned long flags;
int ret;
local_irq_save(flags);
--v->counter;
ret = v->counter;
@ -76,7 +80,8 @@ static __inline__ int atomic_dec_return(atomic_t *v)
static __inline__ int atomic_dec_and_test(atomic_t *v)
{
int ret,flags;
unsigned long flags;
int ret;
local_irq_save(flags);
--v->counter;
ret = v->counter;

4
arch/h8300/include/asm/system.h
View File

@ -3,6 +3,8 @@
#include <linux/linkage.h>
struct pt_regs;
/*
* switch_to(n) should switch tasks to task ptr, first checking that
* ptr isn't the current task, in which case it does nothing. This
@ -155,6 +157,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
#define arch_align_stack(x) (x)
void die(char *str, struct pt_regs *fp, unsigned long err);
extern void die(const char *str, struct pt_regs *fp, unsigned long err);
#endif /* _H8300_SYSTEM_H */

4
arch/h8300/kernel/sys_h8300.c
View File

@ -56,8 +56,8 @@ int kernel_execve(const char *filename,
const char *const envp[])
{
register long res __asm__("er0");
register char *const *_c __asm__("er3") = envp;
register char *const *_b __asm__("er2") = argv;
register const char *const *_c __asm__("er3") = envp;
register const char *const *_b __asm__("er2") = argv;
register const char * _a __asm__("er1") = filename;
__asm__ __volatile__ ("mov.l %1,er0\n\t"
"trapa #0\n\t"

2
arch/h8300/kernel/traps.c
View File

@ -96,7 +96,7 @@ static void dump(struct pt_regs *fp)
printk("\n\n");
}
void die(char *str, struct pt_regs *fp, unsigned long err)
void die(const char *str, struct pt_regs *fp, unsigned long err)
{
static int diecount;

2
arch/ia64/hp/sim/simserial.c
View File

@ -149,7 +149,7 @@ static void receive_chars(struct tty_struct *tty)
ch = ia64_ssc(0, 0, 0, 0,
SSC_GETCHAR);
while (!ch);
handle_sysrq(ch, NULL);
handle_sysrq(ch);
}
#endif
seen_esc = 0;

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