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pwm: Add Broadcom BCM7038 PWM controller support
Add support for the BCM7038-style PWM controller found in all BCM7xxx STB SoCs. This controller has a hardcoded 2 channels per controller, and cascades a variable frequency generator on top of a fixed frequency generator which offers a range of a 148ns period all the way to ~622ms periods. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Florian Fainelli
Thierry Reding
parent
9495525e51
commit
3a9f595702
@ -110,6 +110,16 @@ config PWM_BFIN
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To compile this driver as a module, choose M here: the module
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will be called pwm-bfin.
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config PWM_BRCMSTB
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tristate "Broadcom STB PWM support"
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depends on ARCH_BRCMSTB || BMIPS_GENERIC
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help
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Generic PWM framework driver for the Broadcom Set-top-Box
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SoCs (BCM7xxx).
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To compile this driver as a module, choose M Here: the module
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will be called pwm-brcmstb.c.
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config PWM_CLPS711X
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tristate "CLPS711X PWM support"
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depends on ARCH_CLPS711X || COMPILE_TEST
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@ -8,6 +8,7 @@ obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o
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obj-$(CONFIG_PWM_BCM2835) += pwm-bcm2835.o
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obj-$(CONFIG_PWM_BERLIN) += pwm-berlin.o
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obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
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obj-$(CONFIG_PWM_BRCMSTB) += pwm-brcmstb.o
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obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o
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obj-$(CONFIG_PWM_CRC) += pwm-crc.o
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obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o
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343
drivers/pwm/pwm-brcmstb.c
Normal file
343
drivers/pwm/pwm-brcmstb.c
Normal file
@ -0,0 +1,343 @@
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/*
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* Broadcom BCM7038 PWM driver
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* Author: Florian Fainelli
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*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/spinlock.h>
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#define PWM_CTRL 0x00
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#define CTRL_START BIT(0)
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#define CTRL_OEB BIT(1)
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#define CTRL_FORCE_HIGH BIT(2)
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#define CTRL_OPENDRAIN BIT(3)
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#define CTRL_CHAN_OFFS 4
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#define PWM_CTRL2 0x04
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#define CTRL2_OUT_SELECT BIT(0)
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#define PWM_CH_SIZE 0x8
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#define PWM_CWORD_MSB(ch) (0x08 + ((ch) * PWM_CH_SIZE))
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#define PWM_CWORD_LSB(ch) (0x0c + ((ch) * PWM_CH_SIZE))
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/* Number of bits for the CWORD value */
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#define CWORD_BIT_SIZE 16
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/*
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* Maximum control word value allowed when variable-frequency PWM is used as a
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* clock for the constant-frequency PMW.
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*/
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#define CONST_VAR_F_MAX 32768
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#define CONST_VAR_F_MIN 1
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#define PWM_ON(ch) (0x18 + ((ch) * PWM_CH_SIZE))
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#define PWM_ON_MIN 1
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#define PWM_PERIOD(ch) (0x1c + ((ch) * PWM_CH_SIZE))
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#define PWM_PERIOD_MIN 0
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#define PWM_ON_PERIOD_MAX 0xff
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struct brcmstb_pwm {
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void __iomem *base;
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spinlock_t lock;
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struct clk *clk;
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struct pwm_chip chip;
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};
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static inline u32 brcmstb_pwm_readl(struct brcmstb_pwm *p,
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unsigned int offset)
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{
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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return __raw_readl(p->base + offset);
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else
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return readl_relaxed(p->base + offset);
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}
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static inline void brcmstb_pwm_writel(struct brcmstb_pwm *p, u32 value,
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unsigned int offset)
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{
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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__raw_writel(value, p->base + offset);
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else
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writel_relaxed(value, p->base + offset);
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}
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static inline struct brcmstb_pwm *to_brcmstb_pwm(struct pwm_chip *chip)
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{
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return container_of(chip, struct brcmstb_pwm, chip);
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}
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/*
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* Fv is derived from the variable frequency output. The variable frequency
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* output is configured using this formula:
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*
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* W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
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*
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* Fv = W x 2 ^ -16 x 27Mhz (reference clock)
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*
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* The period is: (period + 1) / Fv and "on" time is on / (period + 1)
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*
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* The PWM core framework specifies that the "duty_ns" parameter is in fact the
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* "on" time, so this translates directly into our HW programming here.
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*/
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static int brcmstb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
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unsigned long pc, dc, cword = CONST_VAR_F_MAX;
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unsigned int channel = pwm->hwpwm;
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u32 value;
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/*
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* If asking for a duty_ns equal to period_ns, we need to substract
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* the period value by 1 to make it shorter than the "on" time and
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* produce a flat 100% duty cycle signal, and max out the "on" time
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*/
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if (duty_ns == period_ns) {
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dc = PWM_ON_PERIOD_MAX;
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pc = PWM_ON_PERIOD_MAX - 1;
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goto done;
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}
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while (1) {
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u64 rate, tmp;
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/*
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* Calculate the base rate from base frequency and current
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* cword
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*/
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rate = (u64)clk_get_rate(p->clk) * (u64)cword;
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do_div(rate, 1 << CWORD_BIT_SIZE);
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tmp = period_ns * rate;
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do_div(tmp, NSEC_PER_SEC);
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pc = tmp;
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tmp = (duty_ns + 1) * rate;
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do_div(tmp, NSEC_PER_SEC);
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dc = tmp;
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/*
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* We can be called with separate duty and period updates,
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* so do not reject dc == 0 right away
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*/
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if (pc == PWM_PERIOD_MIN || (dc < PWM_ON_MIN && duty_ns))
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return -EINVAL;
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/* We converged on a calculation */
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if (pc <= PWM_ON_PERIOD_MAX && dc <= PWM_ON_PERIOD_MAX)
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break;
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/*
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* The cword needs to be a power of 2 for the variable
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* frequency generator to output a 50% duty cycle variable
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* frequency which is used as input clock to the fixed
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* frequency generator.
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*/
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cword >>= 1;
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/*
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* Desired periods are too large, we do not have a divider
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* for them
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*/
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if (cword < CONST_VAR_F_MIN)
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return -EINVAL;
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}
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done:
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/*
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* Configure the defined "cword" value to have the variable frequency
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* generator output a base frequency for the constant frequency
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* generator to derive from.
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*/
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spin_lock(&p->lock);
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brcmstb_pwm_writel(p, cword >> 8, PWM_CWORD_MSB(channel));
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brcmstb_pwm_writel(p, cword & 0xff, PWM_CWORD_LSB(channel));
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/* Select constant frequency signal output */
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value = brcmstb_pwm_readl(p, PWM_CTRL2);
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value |= CTRL2_OUT_SELECT << (channel * CTRL_CHAN_OFFS);
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brcmstb_pwm_writel(p, value, PWM_CTRL2);
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/* Configure on and period value */
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brcmstb_pwm_writel(p, pc, PWM_PERIOD(channel));
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brcmstb_pwm_writel(p, dc, PWM_ON(channel));
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spin_unlock(&p->lock);
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return 0;
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}
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static inline void brcmstb_pwm_enable_set(struct brcmstb_pwm *p,
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unsigned int channel, bool enable)
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{
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unsigned int shift = channel * CTRL_CHAN_OFFS;
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u32 value;
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spin_lock(&p->lock);
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value = brcmstb_pwm_readl(p, PWM_CTRL);
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if (enable) {
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value &= ~(CTRL_OEB << shift);
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value |= (CTRL_START | CTRL_OPENDRAIN) << shift;
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} else {
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value &= ~((CTRL_START | CTRL_OPENDRAIN) << shift);
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value |= CTRL_OEB << shift;
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}
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brcmstb_pwm_writel(p, value, PWM_CTRL);
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spin_unlock(&p->lock);
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}
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static int brcmstb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
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brcmstb_pwm_enable_set(p, pwm->hwpwm, true);
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return 0;
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}
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static void brcmstb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
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brcmstb_pwm_enable_set(p, pwm->hwpwm, false);
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}
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static const struct pwm_ops brcmstb_pwm_ops = {
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.config = brcmstb_pwm_config,
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.enable = brcmstb_pwm_enable,
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.disable = brcmstb_pwm_disable,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id brcmstb_pwm_of_match[] = {
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{ .compatible = "brcm,bcm7038-pwm", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, brcmstb_pwm_of_match);
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static int brcmstb_pwm_probe(struct platform_device *pdev)
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{
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struct brcmstb_pwm *p;
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struct resource *res;
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int ret;
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p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
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if (!p)
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return -ENOMEM;
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spin_lock_init(&p->lock);
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p->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(p->clk)) {
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dev_err(&pdev->dev, "failed to obtain clock\n");
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return PTR_ERR(p->clk);
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}
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ret = clk_prepare_enable(p->clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, p);
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p->chip.dev = &pdev->dev;
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p->chip.ops = &brcmstb_pwm_ops;
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p->chip.base = -1;
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p->chip.npwm = 2;
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p->chip.can_sleep = true;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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p->base = devm_ioremap_resource(&pdev->dev, res);
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if (!p->base) {
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ret = -ENOMEM;
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goto out_clk;
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}
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ret = pwmchip_add(&p->chip);
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if (ret) {
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dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
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goto out_clk;
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}
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return 0;
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out_clk:
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clk_disable_unprepare(p->clk);
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return ret;
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}
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static int brcmstb_pwm_remove(struct platform_device *pdev)
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{
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struct brcmstb_pwm *p = platform_get_drvdata(pdev);
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int ret;
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ret = pwmchip_remove(&p->chip);
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clk_disable_unprepare(p->clk);
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return ret;
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}
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#ifdef CONFIG_PM_SLEEP
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static int brcmstb_pwm_suspend(struct device *dev)
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{
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struct brcmstb_pwm *p = dev_get_drvdata(dev);
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clk_disable(p->clk);
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return 0;
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}
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static int brcmstb_pwm_resume(struct device *dev)
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{
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struct brcmstb_pwm *p = dev_get_drvdata(dev);
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clk_enable(p->clk);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(brcmstb_pwm_pm_ops, brcmstb_pwm_suspend,
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brcmstb_pwm_resume);
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static struct platform_driver brcmstb_pwm_driver = {
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.probe = brcmstb_pwm_probe,
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.remove = brcmstb_pwm_remove,
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.driver = {
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.name = "pwm-brcmstb",
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.of_match_table = brcmstb_pwm_of_match,
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.pm = &brcmstb_pwm_pm_ops,
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},
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};
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module_platform_driver(brcmstb_pwm_driver);
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MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
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MODULE_DESCRIPTION("Broadcom STB PWM driver");
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MODULE_ALIAS("platform:pwm-brcmstb");
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MODULE_LICENSE("GPL");
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