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Blackfin: bf561: rewrite SICA_xxx to just SIC_xxx
This matches all the other Blackfin ports and keep us from having to write bf561-specific code in many places. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
9ebcaa47ba
commit
39c999697b
@ -29,10 +29,10 @@ coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
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switch (cmd) {
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case CMD_COREB_START:
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bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020);
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bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
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break;
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case CMD_COREB_STOP:
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bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020);
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bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020);
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bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
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break;
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case CMD_COREB_RESET:
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@ -24,29 +24,16 @@
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#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
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#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
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#define SIC_IWR0 SICA_IWR0
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#define SIC_IWR1 SICA_IWR1
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#define SIC_IAR0 SICA_IAR0
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#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
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#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
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#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0
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#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1
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#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0
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#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1
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#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
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#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
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#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
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#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
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#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
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#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
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#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2))
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#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val)
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#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
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#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
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#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2))
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#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val)
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/* Weird muxer funcs which pick SIC regs from IMASK base */
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#define __SIC_MUX(base, x) ((base) + ((x) << 2))
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#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x))
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#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
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#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))
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#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
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#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))
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#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
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#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
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#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
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#define BFIN_UART_NR_PORTS 1
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@ -30,49 +30,41 @@
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#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
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#define bfin_read_CHIPID() bfin_read32(CHIPID)
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/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
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#define bfin_read_SWRST() bfin_read_SICA_SWRST()
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#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
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#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
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#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
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/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
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#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
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#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val)
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#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR)
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#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val)
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#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT)
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#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val)
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#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK)
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#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val)
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#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0)
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#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val)
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#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1)
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#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val)
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#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0)
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#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val)
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#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1)
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#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val)
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#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2)
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#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val)
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#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3)
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#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val)
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#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4)
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#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val)
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#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5)
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#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val)
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#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6)
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#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val)
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#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7)
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#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val)
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#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0)
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#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val)
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#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1)
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#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val)
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#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0)
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#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val)
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#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1)
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#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val)
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#define bfin_read_SWRST() bfin_read16(SWRST)
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#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
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#define bfin_read_SYSCR() bfin_read16(SYSCR)
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#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
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#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
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#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val)
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#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
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#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val)
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#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
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#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val)
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#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
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#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
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#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
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#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
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#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
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#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
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#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
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#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
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#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
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#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val)
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#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
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#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val)
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#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
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#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val)
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#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
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#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val)
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#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
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#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val)
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#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
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#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val)
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#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
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#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
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#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
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#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val)
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/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
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#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
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@ -28,32 +28,29 @@
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#define CHIPID 0xFFC00014 /* Chip ID Register */
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/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
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#define SWRST SICA_SWRST
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#define SYSCR SICA_SYSCR
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#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
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#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
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#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
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#define RESET_SOFTWARE (SWRST_OCCURRED)
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/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
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#define SICA_SWRST 0xFFC00100 /* Software Reset register */
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#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */
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#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
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#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */
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#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
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#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
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#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
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#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
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#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
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#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
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#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
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#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
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#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
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#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
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#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
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#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
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#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
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#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
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#define SWRST 0xFFC00100 /* Software Reset register */
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#define SYSCR 0xFFC00104 /* System Reset Configuration register */
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#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
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#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
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#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
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#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
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#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
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#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
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#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
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#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
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#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
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#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
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#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
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#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
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#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
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#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
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#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
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/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
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#define SICB_SWRST 0xFFC01100 /* reserved */
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@ -13,7 +13,7 @@
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void __init program_IAR(void)
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{
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/* Program the IAR0 Register with the configured priority */
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bfin_write_SICA_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
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bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
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((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
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((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) |
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((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) |
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@ -22,7 +22,7 @@ void __init program_IAR(void)
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((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
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((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS));
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bfin_write_SICA_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) |
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bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) |
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((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) |
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((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) |
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((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) |
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@ -31,7 +31,7 @@ void __init program_IAR(void)
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((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) |
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((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS));
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bfin_write_SICA_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) |
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bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) |
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((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) |
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((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) |
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((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) |
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@ -40,7 +40,7 @@ void __init program_IAR(void)
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((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) |
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((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS));
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bfin_write_SICA_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) |
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bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) |
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((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) |
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((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) |
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((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) |
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@ -49,7 +49,7 @@ void __init program_IAR(void)
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((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) |
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((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS));
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bfin_write_SICA_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) |
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bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) |
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((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) |
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((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) |
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((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
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@ -58,7 +58,7 @@ void __init program_IAR(void)
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((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
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((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
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bfin_write_SICA_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
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bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
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((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
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((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
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((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
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@ -67,7 +67,7 @@ void __init program_IAR(void)
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((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) |
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((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS));
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bfin_write_SICA_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) |
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bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) |
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((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) |
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((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) |
|
||||
((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) |
|
||||
@ -76,7 +76,7 @@ void __init program_IAR(void)
|
||||
((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) |
|
||||
((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS));
|
||||
|
||||
bfin_write_SICA_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) |
|
||||
bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) |
|
||||
((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) |
|
||||
((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) |
|
||||
((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) |
|
||||
|
||||
@ -52,19 +52,19 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
|
||||
void __cpuinit platform_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/* Clone setup for peripheral interrupt sources from CoreA. */
|
||||
bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
|
||||
bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
|
||||
bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
|
||||
bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
|
||||
SSYNC();
|
||||
|
||||
/* Clone setup for IARs from CoreA. */
|
||||
bfin_write_SICB_IAR0(bfin_read_SICA_IAR0());
|
||||
bfin_write_SICB_IAR1(bfin_read_SICA_IAR1());
|
||||
bfin_write_SICB_IAR2(bfin_read_SICA_IAR2());
|
||||
bfin_write_SICB_IAR3(bfin_read_SICA_IAR3());
|
||||
bfin_write_SICB_IAR4(bfin_read_SICA_IAR4());
|
||||
bfin_write_SICB_IAR5(bfin_read_SICA_IAR5());
|
||||
bfin_write_SICB_IAR6(bfin_read_SICA_IAR6());
|
||||
bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
|
||||
bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
|
||||
bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
|
||||
bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
|
||||
bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
|
||||
bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
|
||||
bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
|
||||
bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
|
||||
bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
|
||||
bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
|
||||
bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
|
||||
SSYNC();
|
||||
@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
|
||||
|
||||
spin_lock(&boot_lock);
|
||||
|
||||
if ((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0) {
|
||||
if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) {
|
||||
/* CoreB already running, sending ipi to wakeup it */
|
||||
platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
|
||||
} else {
|
||||
/* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
|
||||
bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT);
|
||||
bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT);
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
|
||||
@ -292,13 +292,7 @@ ENTRY(_do_hibernate)
|
||||
#ifdef SIC_IMASK
|
||||
PM_SYS_PUSH(SIC_IMASK)
|
||||
#endif
|
||||
#ifdef SICA_IMASK0
|
||||
PM_SYS_PUSH(SICA_IMASK0)
|
||||
#endif
|
||||
#ifdef SICA_IMASK1
|
||||
PM_SYS_PUSH(SICA_IMASK1)
|
||||
#endif
|
||||
#ifdef SIC_IAR2
|
||||
#ifdef SIC_IAR0
|
||||
PM_SYS_PUSH(SIC_IAR0)
|
||||
PM_SYS_PUSH(SIC_IAR1)
|
||||
PM_SYS_PUSH(SIC_IAR2)
|
||||
@ -321,17 +315,6 @@ ENTRY(_do_hibernate)
|
||||
PM_SYS_PUSH(SIC_IAR11)
|
||||
#endif
|
||||
|
||||
#ifdef SICA_IAR0
|
||||
PM_SYS_PUSH(SICA_IAR0)
|
||||
PM_SYS_PUSH(SICA_IAR1)
|
||||
PM_SYS_PUSH(SICA_IAR2)
|
||||
PM_SYS_PUSH(SICA_IAR3)
|
||||
PM_SYS_PUSH(SICA_IAR4)
|
||||
PM_SYS_PUSH(SICA_IAR5)
|
||||
PM_SYS_PUSH(SICA_IAR6)
|
||||
PM_SYS_PUSH(SICA_IAR7)
|
||||
#endif
|
||||
|
||||
#ifdef SIC_IWR
|
||||
PM_SYS_PUSH(SIC_IWR)
|
||||
#endif
|
||||
@ -344,12 +327,6 @@ ENTRY(_do_hibernate)
|
||||
#ifdef SIC_IWR2
|
||||
PM_SYS_PUSH(SIC_IWR2)
|
||||
#endif
|
||||
#ifdef SICA_IWR0
|
||||
PM_SYS_PUSH(SICA_IWR0)
|
||||
#endif
|
||||
#ifdef SICA_IWR1
|
||||
PM_SYS_PUSH(SICA_IWR1)
|
||||
#endif
|
||||
|
||||
#ifdef PINT0_ASSIGN
|
||||
PM_SYS_PUSH(PINT0_MASK_SET)
|
||||
@ -750,12 +727,6 @@ ENTRY(_do_hibernate)
|
||||
PM_SYS_POP(PINT0_MASK_SET)
|
||||
#endif
|
||||
|
||||
#ifdef SICA_IWR1
|
||||
PM_SYS_POP(SICA_IWR1)
|
||||
#endif
|
||||
#ifdef SICA_IWR0
|
||||
PM_SYS_POP(SICA_IWR0)
|
||||
#endif
|
||||
#ifdef SIC_IWR2
|
||||
PM_SYS_POP(SIC_IWR2)
|
||||
#endif
|
||||
@ -769,17 +740,6 @@ ENTRY(_do_hibernate)
|
||||
PM_SYS_POP(SIC_IWR)
|
||||
#endif
|
||||
|
||||
#ifdef SICA_IAR0
|
||||
PM_SYS_POP(SICA_IAR7)
|
||||
PM_SYS_POP(SICA_IAR6)
|
||||
PM_SYS_POP(SICA_IAR5)
|
||||
PM_SYS_POP(SICA_IAR4)
|
||||
PM_SYS_POP(SICA_IAR3)
|
||||
PM_SYS_POP(SICA_IAR2)
|
||||
PM_SYS_POP(SICA_IAR1)
|
||||
PM_SYS_POP(SICA_IAR0)
|
||||
#endif
|
||||
|
||||
#ifdef SIC_IAR8
|
||||
PM_SYS_POP(SIC_IAR11)
|
||||
PM_SYS_POP(SIC_IAR10)
|
||||
@ -797,17 +757,11 @@ ENTRY(_do_hibernate)
|
||||
#ifdef SIC_IAR3
|
||||
PM_SYS_POP(SIC_IAR3)
|
||||
#endif
|
||||
#ifdef SIC_IAR2
|
||||
#ifdef SIC_IAR0
|
||||
PM_SYS_POP(SIC_IAR2)
|
||||
PM_SYS_POP(SIC_IAR1)
|
||||
PM_SYS_POP(SIC_IAR0)
|
||||
#endif
|
||||
#ifdef SICA_IMASK1
|
||||
PM_SYS_POP(SICA_IMASK1)
|
||||
#endif
|
||||
#ifdef SICA_IMASK0
|
||||
PM_SYS_POP(SICA_IMASK0)
|
||||
#endif
|
||||
#ifdef SIC_IMASK
|
||||
PM_SYS_POP(SIC_IMASK)
|
||||
#endif
|
||||
|
||||
@ -1299,7 +1299,7 @@ void do_irq(int vec, struct pt_regs *fp)
|
||||
} else {
|
||||
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
|
||||
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
|
||||
#if defined(SIC_ISR0) || defined(SICA_ISR0)
|
||||
#if defined(SIC_ISR0)
|
||||
unsigned long sic_status[3];
|
||||
|
||||
if (smp_processor_id()) {
|
||||
@ -1379,7 +1379,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
|
||||
if (likely(vec == EVT_IVTMR_P))
|
||||
irq = IRQ_CORETMR;
|
||||
else {
|
||||
#if defined(SIC_ISR0) || defined(SICA_ISR0)
|
||||
#if defined(SIC_ISR0)
|
||||
unsigned long sic_status[3];
|
||||
|
||||
sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user