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https://mirrors.bfsu.edu.cn/git/linux.git
synced 2025-01-19 12:24:34 +08:00
Merge tag 'gvt-next-2017-02-07' of https://github.com/01org/gvt-linux into drm-intel-next-fixes
From Zhenyu, "These are GVT-g changes for 4.11 merge window, mostly for gvt init order fix that impacted resource handling for device model, the one i915 change has been reviewed and acked." Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
commit
39a75ac4a5
@ -83,7 +83,7 @@ static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
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return 0;
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}
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/* EDID with 1024x768 as its resolution */
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/* EDID with 1920x1200 as its resolution */
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static unsigned char virtual_dp_monitor_edid[] = {
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/*Header*/
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0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
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@ -97,11 +97,16 @@ static unsigned char virtual_dp_monitor_edid[] = {
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0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
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/* Established Timings: maximum resolution is 1024x768 */
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0x21, 0x08, 0x00,
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/* Standard Timings. All invalid */
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0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
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0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
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/* 18 Byte Data Blocks 1: invalid */
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0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
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/*
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* Standard Timings.
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* below new resolutions can be supported:
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* 1920x1080, 1280x720, 1280x960, 1280x1024,
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* 1440x900, 1600x1200, 1680x1050
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*/
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0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
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0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
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/* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
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0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
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0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
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/* 18 Byte Data Blocks 2: invalid */
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0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
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@ -115,7 +120,7 @@ static unsigned char virtual_dp_monitor_edid[] = {
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/* Extension Block Count */
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0x00,
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/* Checksum */
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0xef,
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0x45,
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};
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#define DPCD_HEADER_SIZE 0xb
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@ -48,31 +48,6 @@ struct gvt_firmware_header {
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unsigned char data[1];
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};
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#define RD(offset) (readl(mmio + offset.reg))
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#define WR(v, offset) (writel(v, mmio + offset.reg))
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static void bdw_forcewake_get(void __iomem *mmio)
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{
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WR(_MASKED_BIT_DISABLE(0xffff), FORCEWAKE_MT);
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RD(ECOBUS);
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if (wait_for((RD(FORCEWAKE_ACK_HSW) & FORCEWAKE_KERNEL) == 0, 50))
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gvt_err("fail to wait forcewake idle\n");
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WR(_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL), FORCEWAKE_MT);
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if (wait_for((RD(FORCEWAKE_ACK_HSW) & FORCEWAKE_KERNEL), 50))
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gvt_err("fail to wait forcewake ack\n");
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if (wait_for((RD(GEN6_GT_THREAD_STATUS_REG) &
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GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 50))
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gvt_err("fail to wait c0 wake up\n");
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}
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#undef RD
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#undef WR
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#define dev_to_drm_minor(d) dev_get_drvdata((d))
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static ssize_t
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@ -91,9 +66,9 @@ static struct bin_attribute firmware_attr = {
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.mmap = NULL,
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};
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static int expose_firmware_sysfs(struct intel_gvt *gvt,
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void __iomem *mmio)
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static int expose_firmware_sysfs(struct intel_gvt *gvt)
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{
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struct drm_i915_private *dev_priv = gvt->dev_priv;
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struct intel_gvt_device_info *info = &gvt->device_info;
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struct pci_dev *pdev = gvt->dev_priv->drm.pdev;
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struct intel_gvt_mmio_info *e;
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@ -132,7 +107,7 @@ static int expose_firmware_sysfs(struct intel_gvt *gvt,
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for (j = 0; j < e->length; j += 4)
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*(u32 *)(p + e->offset + j) =
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readl(mmio + e->offset + j);
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I915_READ_NOTRACE(_MMIO(e->offset + j));
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}
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memcpy(gvt->firmware.mmio, p, info->mmio_size);
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@ -235,7 +210,6 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt)
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struct gvt_firmware_header *h;
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const struct firmware *fw;
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char *path;
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void __iomem *mmio;
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void *mem;
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int ret;
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@ -260,17 +234,6 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt)
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firmware->mmio = mem;
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mmio = pci_iomap(pdev, info->mmio_bar, info->mmio_size);
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if (!mmio) {
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kfree(path);
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kfree(firmware->cfg_space);
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kfree(firmware->mmio);
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return -EINVAL;
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}
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if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv))
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bdw_forcewake_get(mmio);
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sprintf(path, "%s/vid_0x%04x_did_0x%04x_rid_0x%04x.golden_hw_state",
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GVT_FIRMWARE_PATH, pdev->vendor, pdev->device,
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pdev->revision);
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@ -300,13 +263,11 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt)
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release_firmware(fw);
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firmware->firmware_loaded = true;
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pci_iounmap(pdev, mmio);
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return 0;
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out_free_fw:
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release_firmware(fw);
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expose_firmware:
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expose_firmware_sysfs(gvt, mmio);
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pci_iounmap(pdev, mmio);
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expose_firmware_sysfs(gvt);
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return 0;
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}
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@ -68,8 +68,6 @@ static const struct intel_gvt_ops intel_gvt_ops = {
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*/
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int intel_gvt_init_host(void)
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{
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int ret;
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if (intel_gvt_host.initialized)
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return 0;
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@ -77,6 +75,13 @@ int intel_gvt_init_host(void)
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if (xen_domain() && !xen_initial_domain())
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return -ENODEV;
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#ifdef CONFIG_INTEL_IOMMU
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if (intel_iommu_gfx_mapped) {
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gvt_err("Hardware IOMMU compatibility not yet supported, try to boot with intel_iommu=igfx_off\n");
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return -ENODEV;
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}
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#endif
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/* Try to load MPT modules for hypervisors */
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if (xen_initial_domain()) {
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/* In Xen dom0 */
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@ -96,11 +101,6 @@ int intel_gvt_init_host(void)
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if (!intel_gvt_host.mpt)
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return -EINVAL;
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/* Try to detect if we're running in host instead of VM. */
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ret = intel_gvt_hypervisor_detect_host();
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if (ret)
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return -ENODEV;
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gvt_dbg_core("Running with hypervisor %s in host mode\n",
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supported_hypervisors[intel_gvt_host.hypervisor_type]);
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@ -38,7 +38,6 @@
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* both Xen and KVM by providing dedicated hypervisor-related MPT modules.
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*/
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struct intel_gvt_mpt {
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int (*detect_host)(void);
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int (*host_init)(struct device *dev, void *gvt, const void *ops);
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void (*host_exit)(struct device *dev, void *gvt);
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int (*attach_vgpu)(void *vgpu, unsigned long *handle);
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@ -1248,43 +1248,6 @@ static void kvmgt_page_track_flush_slot(struct kvm *kvm,
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spin_unlock(&kvm->mmu_lock);
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}
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static bool kvmgt_check_guest(void)
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{
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unsigned int eax, ebx, ecx, edx;
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char s[12];
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unsigned int *i;
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eax = KVM_CPUID_SIGNATURE;
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ebx = ecx = edx = 0;
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asm volatile ("cpuid"
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: "+a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
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:
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: "cc", "memory");
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i = (unsigned int *)s;
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i[0] = ebx;
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i[1] = ecx;
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i[2] = edx;
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return !strncmp(s, "KVMKVMKVM", strlen("KVMKVMKVM"));
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}
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/**
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* NOTE:
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* It's actually impossible to check if we are running in KVM host,
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* since the "KVM host" is simply native. So we only dectect guest here.
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*/
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static int kvmgt_detect_host(void)
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{
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#ifdef CONFIG_INTEL_IOMMU
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if (intel_iommu_gfx_mapped) {
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gvt_err("Hardware IOMMU compatibility not yet supported, try to boot with intel_iommu=igfx_off\n");
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return -ENODEV;
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}
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#endif
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return kvmgt_check_guest() ? -ENODEV : 0;
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}
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static bool __kvmgt_vgpu_exist(struct intel_vgpu *vgpu, struct kvm *kvm)
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{
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struct intel_vgpu *itr;
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@ -1459,7 +1422,6 @@ static unsigned long kvmgt_virt_to_pfn(void *addr)
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}
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struct intel_gvt_mpt kvmgt_mpt = {
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.detect_host = kvmgt_detect_host,
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.host_init = kvmgt_host_init,
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.host_exit = kvmgt_host_exit,
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.attach_vgpu = kvmgt_attach_vgpu,
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@ -43,18 +43,6 @@
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* hypervisor.
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*/
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/**
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* intel_gvt_hypervisor_detect_host - check if GVT-g is running within
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* hypervisor host/privilged domain
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*
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* Returns:
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* Zero on success, -ENODEV if current kernel is running inside a VM
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*/
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static inline int intel_gvt_hypervisor_detect_host(void)
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{
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return intel_gvt_host.mpt->detect_host();
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}
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/**
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* intel_gvt_hypervisor_host_init - init GVT-g host side
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*
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@ -74,7 +74,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
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int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
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{
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unsigned int num_types;
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unsigned int i, low_avail;
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unsigned int i, low_avail, high_avail;
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unsigned int min_low;
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/* vGPU type name is defined as GVTg_Vx_y which contains
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@ -89,9 +89,9 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
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* to indicate how many vGPU instance can be created for this
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* type.
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*
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* Currently use static size here as we init type earlier..
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*/
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low_avail = MB_TO_BYTES(256) - HOST_LOW_GM_SIZE;
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low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
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high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
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num_types = 4;
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gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type),
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@ -106,7 +106,8 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
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gvt->types[i].low_gm_size = min_low;
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gvt->types[i].high_gm_size = max((min_low<<3), MB_TO_BYTES(384U));
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gvt->types[i].fence = 4;
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gvt->types[i].max_instance = low_avail / min_low;
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gvt->types[i].max_instance = min(low_avail / min_low,
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high_avail / gvt->types[i].high_gm_size);
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gvt->types[i].avail_instance = gvt->types[i].max_instance;
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if (IS_GEN8(gvt->dev_priv))
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@ -142,9 +143,9 @@ static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
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/* Need to depend on maxium hw resource size but keep on
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* static config for now.
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*/
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low_gm_avail = MB_TO_BYTES(256) - HOST_LOW_GM_SIZE -
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low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE -
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gvt->gm.vgpu_allocated_low_gm_size;
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high_gm_avail = MB_TO_BYTES(256) * 8UL - HOST_HIGH_GM_SIZE -
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high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE -
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gvt->gm.vgpu_allocated_high_gm_size;
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fence_avail = gvt_fence_sz(gvt) - HOST_FENCE -
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gvt->fence.vgpu_allocated_fence_num;
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@ -824,10 +824,6 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
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if (ret < 0)
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return ret;
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ret = intel_gvt_init(dev_priv);
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if (ret < 0)
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goto err_workqueues;
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/* This must be called before any calls to HAS_PCH_* */
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intel_detect_pch(dev_priv);
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@ -841,7 +837,7 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
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intel_init_audio_hooks(dev_priv);
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ret = i915_gem_load_init(dev_priv);
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if (ret < 0)
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goto err_gvt;
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goto err_workqueues;
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intel_display_crc_init(dev_priv);
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@ -853,8 +849,6 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
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return 0;
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err_gvt:
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intel_gvt_cleanup(dev_priv);
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err_workqueues:
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i915_workqueues_cleanup(dev_priv);
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return ret;
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@ -1077,6 +1071,10 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
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DRM_DEBUG_DRIVER("can't enable MSI");
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}
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ret = intel_gvt_init(dev_priv);
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if (ret)
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goto out_ggtt;
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return 0;
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out_ggtt:
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@ -1290,6 +1288,8 @@ void i915_driver_unload(struct drm_device *dev)
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intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
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intel_gvt_cleanup(dev_priv);
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i915_driver_unregister(dev_priv);
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drm_vblank_cleanup(dev);
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|
@ -67,6 +67,11 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
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return 0;
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}
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if (intel_vgpu_active(dev_priv)) {
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DRM_DEBUG_DRIVER("GVT-g is disabled for guest\n");
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goto bail;
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}
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if (!is_supported_device(dev_priv)) {
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DRM_DEBUG_DRIVER("Unsupported device. GVT-g is disabled\n");
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goto bail;
|
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|
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Block a user