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MIPS: Malta: Probe interrupt controllers via DT
Probe the CPU, GIC & i8259 interrupt controllers present in the Malta system using device tree. This enables interrupts to be provided to devices using device tree as they are moved over to being probed using it. Since Malta is very configurable it's unknown whether a GIC will be present at compile time. In order to support both cases the malta_dt_shim code is added in order to detect whether a GIC is present, adjusting the DT to route interrupts correctly and nop out the GIC node if no GIC is found. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Kees Cook <keescook@chromium.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14274/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
Ralf Baechle
parent
0051fc2e7b
commit
38ec82fe21
@ -479,6 +479,7 @@ config MIPS_MALTA
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select SYS_SUPPORTS_ZBOOT
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select SYS_SUPPORTS_RELOCATABLE
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select USE_OF
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select LIBFDT
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select ZONE_DMA32 if 64BIT
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select BUILTIN_DTB
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select LIBFDT
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@ -1,5 +1,8 @@
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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/memreserve/ 0x00000000 0x00001000; /* YAMON exception vectors */
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/memreserve/ 0x00001000 0x000ef000; /* YAMON */
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/memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */
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@ -8,4 +11,42 @@
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mti,malta";
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cpu_intc: interrupt-controller {
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gic: interrupt-controller@1bdc0000 {
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compatible = "mti,gic";
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reg = <0x1bdc0000 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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/*
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* Declare the interrupt-parent even though the mti,gic
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* binding doesn't require it, such that the kernel can
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* figure out that cpu_intc is the root interrupt
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* controller & should be probed first.
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*/
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interrupt-parent = <&cpu_intc>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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};
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};
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i8259: interrupt-controller@20 {
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compatible = "intel,i8259";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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@ -17,6 +17,8 @@
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#include <asm/bootinfo.h>
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#include <asm/fw/fw.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/malta.h>
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#include <asm/mips-cm.h>
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#include <asm/page.h>
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#define ROCIT_REG_BASE 0x1f403000
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@ -226,6 +228,80 @@ static void __init append_memory(void *fdt, int root_off)
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panic("Unable to set linux,usable-memory property: %d", err);
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}
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static void __init remove_gic(void *fdt)
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{
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int err, gic_off, i8259_off, cpu_off;
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void __iomem *biu_base;
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uint32_t cpu_phandle, sc_cfg;
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/* if we have a CM which reports a GIC is present, leave the DT alone */
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err = mips_cm_probe();
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if (!err && (read_gcr_gic_status() & CM_GCR_GIC_STATUS_GICEX_MSK))
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return;
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if (malta_scon() == MIPS_REVISION_SCON_ROCIT) {
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/*
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* On systems using the RocIT system controller a GIC may be
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* present without a CM. Detect whether that is the case.
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*/
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biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
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MSC01_BIU_ADDRSPACE_SZ);
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sc_cfg = __raw_readl(biu_base + MSC01_SC_CFG_OFS);
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if (sc_cfg & MSC01_SC_CFG_GICPRES_MSK) {
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/* enable the GIC at the system controller level */
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sc_cfg |= BIT(MSC01_SC_CFG_GICENA_SHF);
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__raw_writel(sc_cfg, biu_base + MSC01_SC_CFG_OFS);
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return;
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}
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}
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gic_off = fdt_node_offset_by_compatible(fdt, -1, "mti,gic");
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if (gic_off < 0) {
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pr_warn("malta-dtshim: unable to find DT GIC node: %d\n",
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gic_off);
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return;
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}
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err = fdt_nop_node(fdt, gic_off);
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if (err)
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pr_warn("malta-dtshim: unable to nop GIC node\n");
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i8259_off = fdt_node_offset_by_compatible(fdt, -1, "intel,i8259");
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if (i8259_off < 0) {
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pr_warn("malta-dtshim: unable to find DT i8259 node: %d\n",
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i8259_off);
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return;
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}
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cpu_off = fdt_node_offset_by_compatible(fdt, -1,
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"mti,cpu-interrupt-controller");
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if (cpu_off < 0) {
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pr_warn("malta-dtshim: unable to find CPU intc node: %d\n",
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cpu_off);
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return;
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}
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cpu_phandle = fdt_get_phandle(fdt, cpu_off);
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if (!cpu_phandle) {
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pr_warn("malta-dtshim: unable to get CPU intc phandle\n");
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return;
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}
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err = fdt_setprop_u32(fdt, i8259_off, "interrupt-parent", cpu_phandle);
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if (err) {
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pr_warn("malta-dtshim: unable to set i8259 interrupt-parent: %d\n",
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err);
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return;
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}
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err = fdt_setprop_u32(fdt, i8259_off, "interrupts", 2);
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if (err) {
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pr_warn("malta-dtshim: unable to set i8259 interrupts: %d\n",
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err);
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return;
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}
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}
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void __init *malta_dt_shim(void *fdt)
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{
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int root_off, len, err;
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@ -251,6 +327,7 @@ void __init *malta_dt_shim(void *fdt)
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return fdt;
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append_memory(fdt_buf, root_off);
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remove_gic(fdt_buf);
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err = fdt_pack(fdt_buf);
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if (err)
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@ -14,11 +14,13 @@
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irqchip/mips-gic.h>
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#include <linux/of_irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/kernel.h>
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#include <linux/random.h>
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@ -37,10 +39,6 @@
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#include <asm/setup.h>
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#include <asm/rtlx.h>
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static void __iomem *_msc01_biu_base;
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static DEFINE_RAW_SPINLOCK(mips_irq_lock);
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static inline int mips_pcibios_iack(void)
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{
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int irq;
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@ -85,49 +83,6 @@ static inline int mips_pcibios_iack(void)
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return irq;
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}
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static inline int get_int(void)
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{
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unsigned long flags;
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int irq;
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raw_spin_lock_irqsave(&mips_irq_lock, flags);
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irq = mips_pcibios_iack();
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/*
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* The only way we can decide if an interrupt is spurious
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* is by checking the 8259 registers. This needs a spinlock
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* on an SMP system, so leave it up to the generic code...
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*/
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raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
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return irq;
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}
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static void malta_hw0_irqdispatch(void)
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{
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int irq;
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irq = get_int();
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if (irq < 0) {
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/* interrupt has already been cleared */
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return;
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}
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do_IRQ(MALTA_INT_BASE + irq);
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#ifdef CONFIG_MIPS_VPE_APSP_API_MT
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if (aprp_hook)
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aprp_hook();
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#endif
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}
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static irqreturn_t i8259_handler(int irq, void *dev_id)
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{
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malta_hw0_irqdispatch();
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return IRQ_HANDLED;
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}
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static void corehi_irqdispatch(void)
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{
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unsigned int intedge, intsteer, pcicmd, pcibadaddr;
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@ -240,12 +195,6 @@ static struct irqaction irq_call = {
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};
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#endif /* CONFIG_MIPS_MT_SMP */
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static struct irqaction i8259irq = {
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.handler = i8259_handler,
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.name = "XT-PIC cascade",
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.flags = IRQF_NO_THREAD,
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};
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static struct irqaction corehi_irqaction = {
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.handler = corehi_handler,
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.name = "CoreHi",
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@ -281,28 +230,10 @@ void __init arch_init_ipiirq(int irq, struct irqaction *action)
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void __init arch_init_irq(void)
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{
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int corehi_irq, i8259_irq;
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int corehi_irq;
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init_i8259_irqs();
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if (!cpu_has_veic)
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mips_cpu_irq_init();
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if (mips_cm_present()) {
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write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
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gic_present = 1;
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} else {
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if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
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_msc01_biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
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MSC01_BIU_ADDRSPACE_SZ);
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gic_present =
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(__raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS) &
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MSC01_SC_CFG_GICPRES_MSK) >>
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MSC01_SC_CFG_GICPRES_SHF;
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}
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}
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if (gic_present)
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pr_debug("GIC present\n");
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i8259_set_poll(mips_pcibios_iack);
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irqchip_init();
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switch (mips_revision_sconid) {
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case MIPS_REVISION_SCON_SOCIT:
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@ -330,18 +261,6 @@ void __init arch_init_irq(void)
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}
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if (gic_present) {
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int i;
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gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, MIPSCPU_INT_GIC,
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MIPS_GIC_IRQ_BASE);
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if (!mips_cm_present()) {
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/* Enable the GIC */
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i = __raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS);
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__raw_writel(i | (0x1 << MSC01_SC_CFG_GICENA_SHF),
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_msc01_biu_base + MSC01_SC_CFG_OFS);
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pr_debug("GIC Enabled\n");
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}
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i8259_irq = MIPS_GIC_IRQ_BASE + GIC_INT_I8259A;
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corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
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} else {
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#if defined(CONFIG_MIPS_MT_SMP)
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@ -361,19 +280,14 @@ void __init arch_init_irq(void)
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arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
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#endif
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if (cpu_has_veic) {
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set_vi_handler(MSC01E_INT_I8259A,
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malta_hw0_irqdispatch);
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set_vi_handler(MSC01E_INT_COREHI,
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corehi_irqdispatch);
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i8259_irq = MSC01E_INT_BASE + MSC01E_INT_I8259A;
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corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
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} else {
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i8259_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_I8259A;
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corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
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}
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}
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setup_irq(i8259_irq, &i8259irq);
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setup_irq(corehi_irq, &corehi_irqaction);
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}
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