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clk: sunxi: Unify oscillator clock
This commit uses the new fixed-rate support on the composite clock to unify osc24M_fixed and osc24M clocks, so it matches the actual hardware. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: replace clk_register_gatable_osc with a call to clk_register_composite]
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@ -33,16 +33,36 @@ static DEFINE_SPINLOCK(clk_lock);
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static void __init sunxi_osc_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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struct clk_fixed_rate *fixed;
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struct clk_gate *gate;
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const char *clk_name = node->name;
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const char *parent;
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void *reg;
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u32 rate;
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reg = of_iomap(node, 0);
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/* allocate fixed-rate and gate clock structs */
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fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
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if (!fixed)
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return;
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate) {
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kfree(fixed);
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return;
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}
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parent = of_clk_get_parent_name(node, 0);
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if (of_property_read_u32(node, "clock-frequency", &rate))
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return;
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clk = clk_register_gate(NULL, clk_name, parent, 0, reg,
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SUNXI_OSC24M_GATE, 0, &clk_lock);
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/* set up gate and fixed rate properties */
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gate->reg = of_iomap(node, 0);
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gate->bit_idx = SUNXI_OSC24M_GATE;
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gate->lock = &clk_lock;
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fixed->fixed_rate = rate;
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clk = clk_register_composite(NULL, clk_name,
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NULL, 0,
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NULL, NULL,
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&fixed->hw, &clk_fixed_rate_ops,
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&gate->hw, &clk_gate_ops,
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CLK_IS_ROOT);
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if (clk) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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@ -380,7 +400,6 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
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/* Matches for of_clk_init */
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static const __initconst struct of_device_id clk_match[] = {
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{.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
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{.compatible = "allwinner,sun4i-osc-clk", .data = sunxi_osc_clk_setup,},
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{}
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};
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