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drm/amdgpu: implement uvd_v7_0_(enc_|)ring_emit_reg_wait v2
Add emit_reg_wait implementation for UVD v7. v2: call new function directly from the existing code Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1241,17 +1241,17 @@ static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, 8);
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}
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static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
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uint32_t data0, uint32_t data1, uint32_t mask)
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static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val, uint32_t mask)
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{
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struct amdgpu_device *adev = ring->adev;
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
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amdgpu_ring_write(ring, data0);
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amdgpu_ring_write(ring, reg << 2);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
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amdgpu_ring_write(ring, data1);
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amdgpu_ring_write(ring, val);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
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amdgpu_ring_write(ring, mask);
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@ -1271,16 +1271,16 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
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/* wait for reg writes */
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data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
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data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
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data1 = lower_32_bits(pd_addr);
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mask = 0xffffffff;
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uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
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uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);
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/* wait for flush */
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data0 = (hub->vm_inv_eng0_ack + eng) << 2;
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data0 = hub->vm_inv_eng0_ack + eng;
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data1 = 1 << vmid;
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mask = 1 << vmid;
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uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
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uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);
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}
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static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
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@ -1298,6 +1298,16 @@ static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
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amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
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}
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static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
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uint32_t reg, uint32_t val,
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uint32_t mask)
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{
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amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
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amdgpu_ring_write(ring, reg << 2);
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amdgpu_ring_write(ring, mask);
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amdgpu_ring_write(ring, val);
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}
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static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned int vmid, unsigned pasid,
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uint64_t pd_addr)
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@ -1308,16 +1318,12 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
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pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
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/* wait for reg writes */
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amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
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amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
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amdgpu_ring_write(ring, 0xffffffff);
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amdgpu_ring_write(ring, lower_32_bits(pd_addr));
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uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
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lower_32_bits(pd_addr), 0xffffffff);
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/* wait for flush */
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amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
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amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
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amdgpu_ring_write(ring, 1 << vmid);
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amdgpu_ring_write(ring, 1 << vmid);
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uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng,
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1 << vmid, 1 << vmid);
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}
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static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
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@ -1676,6 +1682,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
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.begin_use = amdgpu_uvd_ring_begin_use,
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.end_use = amdgpu_uvd_ring_end_use,
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.emit_wreg = uvd_v7_0_ring_emit_wreg,
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.emit_reg_wait = uvd_v7_0_ring_emit_reg_wait,
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};
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static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
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@ -1704,6 +1711,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
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.begin_use = amdgpu_uvd_ring_begin_use,
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.end_use = amdgpu_uvd_ring_end_use,
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.emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
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.emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait,
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};
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static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
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